| Author |
Message |
Al Clark
Guest
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 Posted:
Wed Dec 15, 2004 7:48 pm Post subject:
Quartus II Graphic Editor Anomaly? |
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I have a bdf schematic with some pins labeled DAI[13..1] & and DAI[14], DAI
[15], etc.
I have different pins labeled in a similar fashion for example
IO_Bus[10..0].
I then assigned pins to DAI[1], DAI[2], etc. in the assignment editor.
After I compile, Quartus creates new assignments of my DAI pins to DAI1,
DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc assignments.
Other non-DAI pin assignments keep the brackets, IO_Bus[0], IO_Bus[1]
Why are the brackets dropped in some cases at not in others?
--
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com |
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glen herrmannsfeldt
Guest
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| Posted:
Wed Dec 15, 2004 11:47 pm Post subject:
Re: Quartus II Graphic Editor Anomaly? |
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Al Clark wrote:
| Quote: | I have a bdf schematic with some pins labeled DAI[13..1] & and DAI[14], DAI
[15], etc.
|
(snip)
| Quote: | After I compile, Quartus creates new assignments of my DAI pins to DAI1,
DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc assignments.
(snip) |
| Quote: | Why are the brackets dropped in some cases at not in others?
|
Hopefully someone from Altera will explain it, but I have seen some
effects that seem to be due to compatability with MaxPlus, which as I
understand it assigned names without the brackets.
As I remember .bdf is the MaxPlus extension, and .gdf is the Quartus
extension. Rewrite the file as .gdf and maybe it will work.
The assignments, as I understand it, are stored in a different file.
Sometimes I just edit the assignments file by hand if I can't get it
to work otherwise.
-- glen |
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Al Clark
Guest
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| Posted:
Thu Dec 16, 2004 12:06 am Post subject:
Re: Quartus II Graphic Editor Anomaly? |
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glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in
news:cpq10h$frl$1@gnus01.u.washington.edu:
| Quote: |
Al Clark wrote:
I have a bdf schematic with some pins labeled DAI[13..1] & and
DAI[14], DAI [15], etc.
(snip)
After I compile, Quartus creates new assignments of my DAI pins to
DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc
assignments.
(snip)
Why are the brackets dropped in some cases at not in others?
Hopefully someone from Altera will explain it, but I have seen some
effects that seem to be due to compatability with MaxPlus, which as I
understand it assigned names without the brackets.
As I remember .bdf is the MaxPlus extension, and .gdf is the Quartus
extension. Rewrite the file as .gdf and maybe it will work.
The assignments, as I understand it, are stored in a different file.
Sometimes I just edit the assignments file by hand if I can't get it
to work otherwise.
-- glen
|
bdf is the Quartus version, gdf is the older MaxPlus version. The files
are in bdf format. I did have the MaxPlus menu turn on in Configure. I
have since changed to the Quartus style menu, but I don't know if the
problem went away.
I didn't have any problem making the files work by renaming, I just don't
like fixes that I don't understand.
I didn't even see the problem until I looked at the pinout file. I
couldn't get the right signals at DAI[20] etc because the system
automatically created and assigned DAI20 to an unused pin (and left the
original DAI[20] untouched)
--
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com |
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Subroto Datta
Guest
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| Posted:
Thu Dec 16, 2004 1:07 am Post subject:
Re: Quartus II Graphic Editor Anomaly? |
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Al Clark wrote:
| Quote: | glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in
news:cpq10h$frl$1@gnus01.u.washington.edu:
Al Clark wrote:
I have a bdf schematic with some pins labeled DAI[13..1] & and
DAI[14], DAI [15], etc.
(snip)
After I compile, Quartus creates new assignments of my DAI pins to
DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc
assignments.
(snip)
Available at http://www.danvillesignal.com
|
Hi Nate,
BDF is the Quartus extension for the schematic editor while GDF is
the Max+Plus II version of the schematic editor. The netlist extractor
semantics are the same for both of the editors. Backwards compatibility
between Max+Plus II and Quartus for schematic editing and extraction is
a key goal, as there are lots of legacy schematics that have been and
are being transferred to Quartus from Max+Plus II.
Basically the behavior you describe ([] being dropped, and the name
recreated without []) can occur in one or more of the following cases.
1. Some members of a group are of type input and some of type output.
e.g.
A[0..11] is a input and A[12] is an output. In that case the bus is
stored internally as individual bits and the bits are named A0, A1...,
A12.
2. Some members of a group do not exist. e.g. I have A[0..5] and
A[7..12] but A[6] is missing. In that case the bus is stored internally
as individual bits and the bits are named A0, A1..., A12.
3. The user has mixed notation in their design. e.g. I have used both
A[5] and A5 in the same schematic. In that case it will be stored
internally as A5.
If you are not sure which case applies to your schematic, do send your
design over and we can take a look.
The best way to ensure that the pin names used to make assignments
exist is to first compile the design through Process->Start Analysis
and Synthesis. Then use the View->Node Finder and use the Pins filter
to find the node names for pin assignments. These names may be dragged
into the Assignment Editor. Alternatively the Assignment Editor Drop
Down in the To field will show the names that can be used for Pin
Assignment.
Hope this helps,
- Subroto Datta
Altera Corp. |
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Al Clark
Guest
|
| Posted:
Thu Dec 16, 2004 1:23 am Post subject:
Re: Quartus II Graphic Editor Anomaly? |
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"Subroto Datta" <sdatta@altera.com> wrote in news:1103141267.156862.5200
@z14g2000cwz.googlegroups.com:
| Quote: | Al Clark wrote:
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in
news:cpq10h$frl$1@gnus01.u.washington.edu:
Al Clark wrote:
I have a bdf schematic with some pins labeled DAI[13..1] & and
DAI[14], DAI [15], etc.
(snip)
After I compile, Quartus creates new assignments of my DAI pins to
DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc
assignments.
(snip)
Available at http://www.danvillesignal.com
Hi Nate,
BDF is the Quartus extension for the schematic editor while GDF is
the Max+Plus II version of the schematic editor. The netlist extractor
semantics are the same for both of the editors. Backwards compatibility
between Max+Plus II and Quartus for schematic editing and extraction is
a key goal, as there are lots of legacy schematics that have been and
are being transferred to Quartus from Max+Plus II.
Basically the behavior you describe ([] being dropped, and the name
recreated without []) can occur in one or more of the following cases.
1. Some members of a group are of type input and some of type output.
e.g.
A[0..11] is a input and A[12] is an output. In that case the bus is
stored internally as individual bits and the bits are named A0, A1...,
A12.
|
This is the case for my example.
| Quote: |
2. Some members of a group do not exist. e.g. I have A[0..5] and
A[7..12] but A[6] is missing. In that case the bus is stored internally
as individual bits and the bits are named A0, A1..., A12.
|
Maybe also true
| Quote: | 3. The user has mixed notation in their design. e.g. I have used both
A[5] and A5 in the same schematic. In that case it will be stored
internally as A5.
If you are not sure which case applies to your schematic, do send your
design over and we can take a look.
The best way to ensure that the pin names used to make assignments
exist is to first compile the design through Process->Start Analysis
and Synthesis. Then use the View->Node Finder and use the Pins filter
to find the node names for pin assignments. These names may be dragged
into the Assignment Editor. Alternatively the Assignment Editor Drop
Down in the To field will show the names that can be used for Pin
Assignment.
Hope this helps,
- Subroto Datta
Altera Corp.
|
Thank you for your explanation. Can you tell me where this information is
in your documentation?
I have a new question:
I have unused inputs that may be used in a future design. They must be
inputs to avoid contention with other devices. I assigned the pin as a
reserved input in the assignment editor and also individually assigned it
as an tri input. Will the pullup be present? If not, how do I assign an
unused pin as an input with a pullup. I am using a Cyclone.
--
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com |
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