| Author |
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Symon
Guest
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 Posted:
Fri Dec 17, 2004 6:48 pm Post subject:
Re: Digital clock synthesis |
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Hi Ray,
That's what I meant. Make the accumulator modulo 100,000,000. I didn't
mention truncation, I wrote overflow. In fact, I'm struggling to understand
what you think I meant that would mean truncation. What did you mean?
Extending the width of the accumulator doesn't help you get *exactly* the
right frequency if you want 1Hz steps from a 100MHz clock, which is what Hal
was talking about. You just get closer and closer approximations as the
accumulator gets wider. The maximum jitter over the frequency output range
is determined by the clock rate.
Cheers, Syms.
"Ray Andraka" <ray@andraka.com> wrote in message
news:dUAwd.1205$Tf5.139@lakeread03...
| Quote: | Symon wrote:
Hal,
Make the accumulator overflow at 100,000,000 rather than at 134217728.
HTH, Syms.
No, that doesn't work. The phase accumulator depends on modularity of the
number system, and by truncating the count like that you destroy the
modularity. The way to get there is to extend the width of the
accumulator and select the appropriate constant based on the accumulator
width.
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Symon
Guest
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| Posted:
Fri Dec 17, 2004 6:52 pm Post subject:
Re: Digital clock synthesis |
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Why not make the accumulator work modulo 100,000,000? You get exactly 1Hz
and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000 with a
smaller solution?
Cheers, Syms.
"Ray Andraka" <ray@andraka.com> wrote in message
news:aSAwd.1203$Tf5.1052@lakeread03...
| Quote: | You need more than 27 bits. With 27 bits, the resolution is 0.745 Hz. If
you extend it to 32 bits, then you have a frequency resolution of 0.02 Hz
and can therefore get much closer to your 1Hz setting. In that case,
setting the increment value to 43 will yield 1.002 Hz. Increasing the
width of the accumulator improves the frequency resolution. Note that the
jitter is still one cycle of your master clock, so although the frequency
resolution is improved, your jitter is constant.
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Symon
Guest
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| Posted:
Fri Dec 17, 2004 6:57 pm Post subject:
Re: Digital clock synthesis |
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Hmmm, maybe not smaller as you need a subtraction as well as an
accumulation. I need to think about that when I get time. But certainly more
accurate....
"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6k6F3ltb5iU1@individual.net...
| Quote: | Why not make the accumulator work modulo 100,000,000? You get exactly 1Hz
and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000 with
a smaller solution?
Cheers, Syms.
"Ray Andraka" <ray@andraka.com> wrote in message
news:aSAwd.1203$Tf5.1052@lakeread03...
You need more than 27 bits. With 27 bits, the resolution is 0.745 Hz.
If you extend it to 32 bits, then you have a frequency resolution of 0.02
Hz and can therefore get much closer to your 1Hz setting. In that case,
setting the increment value to 43 will yield 1.002 Hz. Increasing the
width of the accumulator improves the frequency resolution. Note that
the jitter is still one cycle of your master clock, so although the
frequency resolution is improved, your jitter is constant.
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John_H
Guest
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| Posted:
Fri Dec 17, 2004 9:29 pm Post subject:
Re: Digital clock synthesis |
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The modulo 100M is just adding either the phase step to the accumulator
(most of the time) or 2^27-100M plus the phase step to the accumulator (each
time the accumulator overflows). Adding a selected one of two values can be
done within the Xilinx carry chain at no cost.
"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6taF3kks5aU1@individual.net...
| Quote: | Hmmm, maybe not smaller as you need a subtraction as well as an
accumulation. I need to think about that when I get time. But certainly
more
accurate....
"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6k6F3ltb5iU1@individual.net...
Why not make the accumulator work modulo 100,000,000? You get exactly
1Hz
and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000
with
a smaller solution?
Cheers, Syms.
"Ray Andraka" <ray@andraka.com> wrote in message
news:aSAwd.1203$Tf5.1052@lakeread03...
You need more than 27 bits. With 27 bits, the resolution is 0.745 Hz.
If you extend it to 32 bits, then you have a frequency resolution of
0.02
Hz and can therefore get much closer to your 1Hz setting. In that
case,
setting the increment value to 43 will yield 1.002 Hz. Increasing the
width of the accumulator improves the frequency resolution. Note that
the jitter is still one cycle of your master clock, so although the
frequency resolution is improved, your jitter is constant. |
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Symon
Guest
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| Posted:
Fri Dec 17, 2004 10:32 pm Post subject:
Re: Digital clock synthesis |
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Hi John,
What I'm thinking is, if the input to the circuit is the phase step,
effectively frequency in this case, you have to calculate "2^27-100M plus
the phase step" somewhere in the circuit each time the frequency changes.
This needs another adder, yes? Can you fit all the stuff into 1 lut per bit?
Cheers, Syms.
"John_H" <johnhandwork@mail.com> wrote in message
news:FPDwd.19$2w4.857@news-west.eli.net...
| Quote: | The modulo 100M is just adding either the phase step to the accumulator
(most of the time) or 2^27-100M plus the phase step to the accumulator
(each
time the accumulator overflows). Adding a selected one of two values can
be
done within the Xilinx carry chain at no cost.
"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6taF3kks5aU1@individual.net...
Hmmm, maybe not smaller as you need a subtraction as well as an
accumulation. I need to think about that when I get time. But certainly
more
accurate....
"Symon" <symon_brewer@hotmail.com> wrote in message
news:32g6k6F3ltb5iU1@individual.net...
Why not make the accumulator work modulo 100,000,000? You get exactly
1Hz
and 1Hz steps. Who wants 1.002 when you can easily have 1.0000000000
with
a smaller solution?
Cheers, Syms. |
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John_H
Guest
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| Posted:
Sat Dec 18, 2004 3:01 am Post subject:
Re: Digital clock synthesis |
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"Symon" <symon_brewer@hotmail.com> wrote in message
news:32gjgiF3lb586U1@individual.net...
| Quote: | Hi John,
What I'm thinking is, if the input to the circuit is the phase step,
effectively frequency in this case, you have to calculate "2^27-100M plus
the phase step" somewhere in the circuit each time the frequency changes.
This needs another adder, yes? Can you fit all the stuff into 1 lut per
bit?
Cheers, Syms.
|
You can have either a separate adder or (as I did it before) two different
phase values supplied by software: the raw phase and the adjusted phase. If
you want an adder to calculate the adjusted phase value, register the value
and the timing doesn't suffer.
Just a reminder that the duty cycle will be (2^26/100M)/(1-2^26/100M) or
67.1%/32.9% on average unless you'd care to adjust whenever the MSbit
toggles. |
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Falk Brunner
Guest
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| Posted:
Sat Dec 18, 2004 4:08 am Post subject:
Re: Digital clock synthesis |
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"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag
news:32g6taF3kks5aU1@individual.net...
| Quote: | Hmmm, maybe not smaller as you need a subtraction as well as an
accumulation. I need to think about that when I get time. But certainly
more
accurate....
|
Why not use a xtal with a power of two frequency?? We telecom guys do this
regulary.
Regards
Falk |
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RobJ
Guest
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| Posted:
Sat Dec 18, 2004 11:16 pm Post subject:
Re: Digital clock synthesis |
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"Ray Andraka" <ray@andraka.com> wrote in message
news:dUAwd.1205$Tf5.139@lakeread03...
| Quote: | Symon wrote:
Hal,
Make the accumulator overflow at 100,000,000 rather than at 134217728.
HTH, Syms.
No, that doesn't work. The phase accumulator depends on modularity of the
number system, and by truncating the count like that you destroy the
modularity. The way to get there is to extend the width of the
accumulator and select the appropriate constant based on the accumulator
width.
Ray - |
I agree for a general-purpose synthesizer with a phase accumulator
addressing
a SINE look-up table. But if you don't need a general-purpose synthesizer
(i.e.,
you only need to generate one output frequency) then can't you pick any
modulus you need and create the SINE LUT to match that modulus?
And if you just need a digital (1-bit) output clock then you should always
be
able to pick whatever accumulator modulus you want and use the MS bit of
the accumulator as the output clock. The only requirements are that
Fout = Fin * (M/N), where M and N are both integers and M/N <= 1/2.
N becomes the modulus of the accumulator and M is the phase value.
For the example being discussed, 1Hz = 100e6Hz*(1/100e6). The modulus
is 100e6, and the phase value is 1. (When the phase value is 1 like this you
can
use a counter instead of an accumulator.) If output duty cycle matters then
you
also need to center the truncated accumulator range in the center of the
full
binary range of the accumulator. In this example you want the accumulator to
cover the range (2^27)/2 -500e6 to (2^27)/2 + 500e6 - 1. The MS bit will
then be a perfect 50% duty cycle 1Hz clock.
Any holes in all this?
Bob S. |
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james
Guest
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| Posted:
Mon Dec 20, 2004 5:56 am Post subject:
Re: Digital clock synthesis |
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On Thu, 16 Dec 2004 04:11:48 -0600, hmurray@suespammers.org (Hal
Murray) wrote:
| Quote: | I can't see how to make a 1 Hz output with a 27 bit phase accumulator
running at 100 MHz. Works great if I have a 134.217728 MHz clock.
If I have a 27 bit accumulator and I add 1 each cycle with a
100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz.
Is there some variation of the simple phase accumulator that I
haven't stumbled into yet? If so, what's the magic word?
********* |
Unless you are dealing with an application that needs a frequency
tolerance of +/- less than 1 Hertz, a 27 bit accumalator and a 100 MHz
clock is quite fine. It is rare in consumer or most industrial
electronics that the frequency generated need be that tight of
tolerance. Even if so then pick a value for your accumalator and match
the crystal that will give you 1 Hz steps.
james |
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