| Author |
Message |
Hal Murray
Guest
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 Posted:
Thu Dec 16, 2004 2:18 am Post subject:
Digital clock synthesis |
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This is leftover from a couple of discussions a week or two ago.
There is something interesting that I don't understand.
In general, if I have an input clock and I want to generate
an output clock, and the output clock is (much) slower than
the input clock, I can do that with a FSM.
The jitter on the output clock can be up to 1/2 of the input
clock off. (If it's off more, move it over by one.) If you
are lucky and the numbers work out exactly, you get no jitter.
(For example, dividing by 4.)
But how close is the frequency? The output frequency is
out = in * X / Y
Y is the number of states in the FSM.
Some combinations of X and Y give a better match to the
target frequency. I'm pretty sure a math wizard would use
continued fractions to explain it.
I know how to implement this if Y is a power of 2. That's
just an adder and it generally fits well into FPGA. Given
a minute or 3, I can work out the value of the constant to
add.
It's easy to get closer to the target frequency by using more
bits in the adder. If the bottom bit of the constant isn't a
1, then the adder will skip 1/2 (or 3/4 or..) of the states.
So there are sweet spots where the bottom bit of the constant
is a 1.
This approach is also convenient if you want to make
a sine wave rather than a square wave since you can
feed the top N bits of the adder to a ROM lookup table.
But powers of 2 may not work as well as some simple pairs
of X and Y. Is there a simple implementation technique
for arbitrary Y that fits well into FPGAs? Is it something
as simple as use an adder and reset it back to 0 after Y
steps?
Is there a good web page or book that covers this area?
Next step is to understand the spectrum of the synthesised
clock.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam. |
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Peter
Guest
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| Posted:
Thu Dec 16, 2004 2:39 am Post subject:
Re: Digital clock synthesis |
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Use Direct Digital Synthesis (DDS) which really means that you
accumulate phase angles.
Think of a 10-bit binary accumulator.
If the value you accumulate is 1, then it will take 1024 clock pulses
to overflow.
If you accumulate a 2, it will take 512 clock ticks etc.
The overflow frequency is thus determined by the 10-bit value you are
accumulating, with a resolution of 1 part in 1024 (but also with a max
jitter of half a clock period.)
With a 27-bit accumulator clocked at 100 MHz, you can generate any
integer Hz frequency, but with 5 ns jitter.
Peter Alfke, Xilinx Applications |
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Falk Brunner
Guest
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| Posted:
Thu Dec 16, 2004 3:41 am Post subject:
Re: Digital clock synthesis |
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"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag
news:beudnbybkd66N13cRVn-qg@megapath.net...
| Quote: | The jitter on the output clock can be up to 1/2 of the input
clock off. (If it's off more, move it over by one.) If you
are lucky and the numbers work out exactly, you get no jitter.
(For example, dividing by 4.)
But how close is the frequency? The output frequency is
out = in * X / Y
Y is the number of states in the FSM.
|
What you describe is called DDS, Direct Digital Synthesis. Go to
www.analog.com, they have plenty of stuff for that. And also a very good
tutorial on the toppic.
| Quote: | This approach is also convenient if you want to make
a sine wave rather than a square wave since you can
feed the top N bits of the adder to a ROM lookup table.
But powers of 2 may not work as well as some simple pairs
of X and Y. Is there a simple implementation technique
for arbitrary Y that fits well into FPGAs? Is it something
|
Again, DDS. It look a little bit weired on the first sight, but then turn
out to a (almost) perfect oscillator.
Regards
Falk |
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John_H
Guest
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| Posted:
Thu Dec 16, 2004 4:43 am Post subject:
Re: Digital clock synthesis |
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You hit on an excellent point, that non binary values of Y indicated below
CAN be easily implemented by adding a different value to the phase
accumulator on one cycle after the phase accumulator overflows. I used this
technique explicitly years ago to avoid some problems, adding a small delta
so I repeated the same phase values over and over. The technique can apply
to fractions with much smaller accumulators with the added benefit of no
very-close-in spurs in your spectrum that can't be filtered out. I put
together an Excel spreadsheet for figuring the best fractions (in order) for
a given value with nice results. It's pretty easy to have a bound value for
most fractions with a very acceptable accuracy without the extremely low
frequency spurs.
The one caution with the overflow-based correction is that 50% duty cycle is
degraded in the simplest implementation. If all you need is an edge or a
pulse, it's great. If you need (closer to) 50%, you need an overflow
correction for each half of the clock cycle.
For X/Y = 12/1021, the phase accumulator normally adds 12 to a 10 bit
accumulator. On overflow, the phase value is "behind" by 3 bits so the
phase accumulator gets 15 added for that round. In 1021 cycles, there are
12 overflows resuling in a phase accumulator value of (1021-12)*12 + 12*15 =
12*1024. Modulo 1024, that's back to 0.
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:beudnbybkd66N13cRVn-qg@megapath.net...
| Quote: | This is leftover from a couple of discussions a week or two ago.
There is something interesting that I don't understand.
In general, if I have an input clock and I want to generate
an output clock, and the output clock is (much) slower than
the input clock, I can do that with a FSM.
The jitter on the output clock can be up to 1/2 of the input
clock off. (If it's off more, move it over by one.) If you
are lucky and the numbers work out exactly, you get no jitter.
(For example, dividing by 4.)
But how close is the frequency? The output frequency is
out = in * X / Y
Y is the number of states in the FSM.
Some combinations of X and Y give a better match to the
target frequency. I'm pretty sure a math wizard would use
continued fractions to explain it.
I know how to implement this if Y is a power of 2. That's
just an adder and it generally fits well into FPGA. Given
a minute or 3, I can work out the value of the constant to
add.
It's easy to get closer to the target frequency by using more
bits in the adder. If the bottom bit of the constant isn't a
1, then the adder will skip 1/2 (or 3/4 or..) of the states.
So there are sweet spots where the bottom bit of the constant
is a 1.
This approach is also convenient if you want to make
a sine wave rather than a square wave since you can
feed the top N bits of the adder to a ROM lookup table.
But powers of 2 may not work as well as some simple pairs
of X and Y. Is there a simple implementation technique
for arbitrary Y that fits well into FPGAs? Is it something
as simple as use an adder and reset it back to 0 after Y
steps?
Is there a good web page or book that covers this area?
Next step is to understand the spectrum of the synthesised
clock.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
commercial e-mail to my suespammers.org address or any of my other
addresses.
These are my opinions, not necessarily my employer's. I hate spam.
|
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Allan Herriman
Guest
|
| Posted:
Thu Dec 16, 2004 10:56 am Post subject:
Re: Digital clock synthesis |
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|
On Wed, 15 Dec 2004 15:18:31 -0600, hmurray@suespammers.org (Hal
Murray) wrote:
| Quote: | This is leftover from a couple of discussions a week or two ago.
There is something interesting that I don't understand.
In general, if I have an input clock and I want to generate
an output clock, and the output clock is (much) slower than
the input clock, I can do that with a FSM.
The jitter on the output clock can be up to 1/2 of the input
clock off. (If it's off more, move it over by one.) If you
are lucky and the numbers work out exactly, you get no jitter.
(For example, dividing by 4.)
|
The peak to peak output jitter at the output can be up to 1 period of
the input clock.
You can use both edges of the input clock to halve this (assuming a
50% duty cycle).
| Quote: | But how close is the frequency? The output frequency is
out = in * X / Y
Y is the number of states in the FSM.
Some combinations of X and Y give a better match to the
target frequency. I'm pretty sure a math wizard would use
continued fractions to explain it.
I know how to implement this if Y is a power of 2. That's
just an adder and it generally fits well into FPGA. Given
a minute or 3, I can work out the value of the constant to
add.
It's easy to get closer to the target frequency by using more
bits in the adder. If the bottom bit of the constant isn't a
1, then the adder will skip 1/2 (or 3/4 or..) of the states.
So there are sweet spots where the bottom bit of the constant
is a 1.
This approach is also convenient if you want to make
a sine wave rather than a square wave since you can
feed the top N bits of the adder to a ROM lookup table.
But powers of 2 may not work as well as some simple pairs
of X and Y. Is there a simple implementation technique
for arbitrary Y that fits well into FPGAs?
|
Yes.
The phase accumulator will always produce a frequency of the form
c
--------------- * Fin
(2 ** num_bits)
As you point out, increasing num_bits improves the accuracy, but can
never give an exact result for some ratios.
There's a different archicture that produces a frequency of the form:
(a + b)
----------------------- * Fin
(a * n) + (b * (n + 1))
This uses a dual modulus prescaler that divides the input clock by
either n or n+1. An FSM twiddles the control of the prescaler to
produce the correct average division.
For a lot of practical ratios (such as those met in telecommunications
circuits) this can produce the exact ratio with the minimum jitter,
often using fewer flip flops than a comparable phase accumulator
solution.
| Quote: | Is there a good web page or book that covers this area?
|
http://fractional-divider.tripod.com/
contains a perl script that works out the nasty details for you, then
generates synthesisable VHDL and Verilog code.
Disclaimer: I wrote the script.
| Quote: | Next step is to understand the spectrum of the synthesised
clock.
|
That's a little tricky, but can be done.
Regards,
Allan |
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Hal Murray
Guest
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| Posted:
Thu Dec 16, 2004 3:11 pm Post subject:
Re: Digital clock synthesis |
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|
| Quote: | With a 27-bit accumulator clocked at 100 MHz, you can generate any
integer Hz frequency, but with 5 ns jitter.
|
Thanks, but that looks like a variation on what I was asking about.
I can't see how to make a 1 Hz output with a 27 bit phase accumulator
running at 100 MHz. Works great if I have a 134.217728 MHz clock.
If I have a 27 bit accumulator and I add 1 each cycle with a
100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz.
Is there some variation of the simple phase accumulator that I
haven't stumbled into yet? If so, what's the magic word?
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam. |
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Symon
Guest
|
| Posted:
Thu Dec 16, 2004 3:16 pm Post subject:
Re: Digital clock synthesis |
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|
Hal,
Make the accumulator overflow at 100,000,000 rather than at 134217728.
HTH, Syms.
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:G8udnZiTqfj5wlzcRVn-2g@megapath.net...
| Quote: | With a 27-bit accumulator clocked at 100 MHz, you can generate any
integer Hz frequency, but with 5 ns jitter.
Thanks, but that looks like a variation on what I was asking about.
I can't see how to make a 1 Hz output with a 27 bit phase accumulator
running at 100 MHz. Works great if I have a 134.217728 MHz clock.
If I have a 27 bit accumulator and I add 1 each cycle with a
100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz.
Is there some variation of the simple phase accumulator that I
haven't stumbled into yet? If so, what's the magic word? |
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Hal Murray
Guest
|
| Posted:
Thu Dec 16, 2004 3:26 pm Post subject:
Re: Digital clock synthesis |
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| Quote: | What you describe is called DDS, Direct Digital Synthesis. Go to
www.analog.com, they have plenty of stuff for that. And also a very good
tutorial on the toppic.
|
Thanks. In case anybody else gets curious:
Ask The Application Engineer-33
All About Direct Digital Synthesis
http://www.analog.com/library/analogDialogue/archives/38-08/dds.html
A Technical Tutorial on Digital Signal Synthesis (120 pages)
http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_rev12-2-99.pdf
(I haven't read it carefully yet. Lots of good stuff.)
| Quote: | But powers of 2 may not work as well as some simple pairs
of X and Y. Is there a simple implementation technique
for arbitrary Y that fits well into FPGAs? Is it something
Again, DDS. It look a little bit weired on the first sight, but then turn
out to a (almost) perfect oscillator.
|
How do I implement a phase accumulator if Y is not a power of 2?
Suppose I want an output that is exactly 4/17 of the input.
That's almost a divide by 4. Just need to insert an extra
stutter every 17 cycles. I can do that with a 17 state FSM.
(34 states gets DC ballance.)
For the simple phase accumulator, the magic number to add
is 0.3C3C3C3... (hex, decimal point on the left edge)
That's a repeating fraction. Making the accumulator bigger
will get closer, but never an exact match. Yet a simple
17 state FSM is right on. Is there a term for something
like that? Is there an easy way to implement them?
(Simpler than a table driven FSM for large numbers of states.)
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam. |
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Symon
Guest
|
| Posted:
Thu Dec 16, 2004 3:43 pm Post subject:
Re: Digital clock synthesis |
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|
Hal,
For 4/17 you should implement
accum <= (accum + 4) mod 17;
Generate your output enable with an overflow signal.
Cheers, Syms.
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:ufWdnSQ3WaVF_1zcRVn-rg@megapath.net...
| Quote: |
How do I implement a phase accumulator if Y is not a power of 2?
Suppose I want an output that is exactly 4/17 of the input.
That's almost a divide by 4. Just need to insert an extra
stutter every 17 cycles. I can do that with a 17 state FSM.
(34 states gets DC ballance.)
|
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Hal Murray
Guest
|
| Posted:
Thu Dec 16, 2004 3:45 pm Post subject:
Re: Digital clock synthesis |
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| Quote: | Make the accumulator overflow at 100,000,000 rather than at 134217728.
|
Ahh. That seems like a key idea. Is there a name/term for this
variation?
I've been stuck in the rut of thinking of the decimal point
to the left of the accumulator. The top bit is the output
if you want a square wave. Use the top N bits and a ROM
if you want a sine wave.
If I want a 50% duty cycle, I think I have to move the decimal
point 1 step to the right and "overflow" the fraction at 50,000,000.
Move it more for the sine/ROM trick. Or something like that.
But that's just a scaling factor.
I still don't see how to easily implement "overflow" at an
arbitrary value. Time to sleep on it.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam. |
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Symon
Guest
|
| Posted:
Thu Dec 16, 2004 3:58 pm Post subject:
Re: Digital clock synthesis |
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|
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:0qadncXIAdX6-lzcRVn-ig@megapath.net...
| Quote: | Make the accumulator overflow at 100,000,000 rather than at 134217728.
Ahh. That seems like a key idea. Is there a name/term for this
variation?
I've been stuck in the rut of thinking of the decimal point
to the left of the accumulator. The top bit is the output
if you want a square wave. Use the top N bits and a ROM
if you want a sine wave.
If I want a 50% duty cycle, I think I have to move the decimal
point 1 step to the right and "overflow" the fraction at 50,000,000.
Move it more for the sine/ROM trick. Or something like that.
But that's just a scaling factor.
How about:- |
if accum < 50000000 then
accum <= accum + freq;
else
accum <= accum + freq - 50000000;
out <= not out;
end if;
| Quote: | I still don't see how to easily implement "overflow" at an
arbitrary value. Time to sleep on it.
I thought you were up late! I'm on a trip to the UK; time for lunch! |
best, Syms. |
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Kolja Sulimma
Guest
|
| Posted:
Thu Dec 16, 2004 5:23 pm Post subject:
Re: Digital clock synthesis |
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John_H wrote:
| Quote: | You hit on an excellent point, that non binary values of Y indicated below
CAN be easily implemented by adding a different value to the phase
accumulator on one cycle after the phase accumulator overflows.
|
This is essentially Bresenhams algorithm for line drawing:
http://www.cs.helsinki.fi/group/goa/mallinnus/lines/bresenh.html
Bresenham is used to draw a line that moves up by dy pixels while going
to the right for dx pixels. You can easily translate it to generating dy
clock output transitions during dx clock cycles.
The algorithm produces provably minimum error.
Kolja Sulimma |
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glen herrmannsfeldt
Guest
|
| Posted:
Thu Dec 16, 2004 11:07 pm Post subject:
Re: Digital clock synthesis |
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Hal Murray wrote:
(someone wrote)
| Quote: | Make the accumulator overflow at 100,000,000 rather than at 134217728.
|
(snip)
| Quote: | I still don't see how to easily implement "overflow" at an
arbitrary value. Time to sleep on it.
|
On overflow load 34117728 into the counter instead of 0.
-- glen |
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Ray Andraka
Guest
|
| Posted:
Fri Dec 17, 2004 6:09 pm Post subject:
Re: Digital clock synthesis |
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|
Hal Murray wrote:
| Quote: | With a 27-bit accumulator clocked at 100 MHz, you can generate any
integer Hz frequency, but with 5 ns jitter.
Thanks, but that looks like a variation on what I was asking about.
I can't see how to make a 1 Hz output with a 27 bit phase accumulator
running at 100 MHz. Works great if I have a 134.217728 MHz clock.
If I have a 27 bit accumulator and I add 1 each cycle with a
100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz.
Is there some variation of the simple phase accumulator that I
haven't stumbled into yet? If so, what's the magic word?
You need more than 27 bits. With 27 bits, the resolution is 0.745 Hz. |
If you extend it to 32 bits, then you have a frequency resolution of
0.02 Hz and can therefore get much closer to your 1Hz setting. In that
case, setting the increment value to 43 will yield 1.002 Hz. Increasing
the width of the accumulator improves the frequency resolution. Note
that the jitter is still one cycle of your master clock, so although the
frequency resolution is improved, your jitter is constant.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759 |
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Ray Andraka
Guest
|
| Posted:
Fri Dec 17, 2004 6:11 pm Post subject:
Re: Digital clock synthesis |
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|
Symon wrote:
| Quote: | Hal,
Make the accumulator overflow at 100,000,000 rather than at 134217728.
HTH, Syms.
No, that doesn't work. The phase accumulator depends on modularity of |
the number system, and by truncating the count like that you destroy the
modularity. The way to get there is to extend the width of the
accumulator and select the appropriate constant based on the accumulator
width.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759 |
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