| Author |
Message |
Martijn
Guest
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 Posted:
Thu Dec 16, 2004 4:03 pm Post subject:
Looking for a SIMD DSP |
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Hello,
I am looking for a SIMD or Vector DSP, and I was hoping some of the
people here could recommend one.
The processor I am looking for should support memory accesses with
stride and a summation reduction operation.
So far I found the eLite processor from IBM, but as I understand it, it
is still under development.
Furthermore some old supercomputers like the MasPar MP-1 support the
features that I need, but I would like to find something that fits on a
single chip and is commercially available.
The problem seems to be the memory accesses with stride. I know the
VIRAM supports it, but it lacks the summation reduction operation.
I know I could emulate the memory access with stride by just reading
(or writing) each vector element from (or to) memory. And the summation
reduction operation could also be emulated by just adding all the
vector elements up.
But this would destroy the scalability of a program I designed (on
paper).
I would like to test this program on a real processor, and to maintain
the scalability both features should be O(1) operations.
(I know I am cheating a bit on the reduction operation, that one is
actually O(log N), even in hardware.)
So if some of you could recommend a processor I would be very grateful.
Thanks,
Martijn v/d Horst |
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Bhaskar Thiagarajan
Guest
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| Posted:
Thu Dec 16, 2004 10:09 pm Post subject:
Re: Looking for a SIMD DSP |
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"Martijn" <martijn.dsp@mailinator.com> wrote in message
news:1103195001.688280.129090@c13g2000cwb.googlegroups.com...
| Quote: | Hello,
I am looking for a SIMD or Vector DSP, and I was hoping some of the
people here could recommend one.
The processor I am looking for should support memory accesses with
stride and a summation reduction operation.
|
I'm not really sure what you mean by "memory accesses with stride" and
"summation reduction operation".
The 2116x Sharcs from Analog Devices are SIMD devices and can support memory
accesses with increment of the pointer (most DSPs do this).
You'd have explain what you mean by the 2 requirements to get more
suggestions.
Cheers
Bhaskar
| Quote: |
So far I found the eLite processor from IBM, but as I understand it, it
is still under development.
Furthermore some old supercomputers like the MasPar MP-1 support the
features that I need, but I would like to find something that fits on a
single chip and is commercially available.
The problem seems to be the memory accesses with stride. I know the
VIRAM supports it, but it lacks the summation reduction operation.
I know I could emulate the memory access with stride by just reading
(or writing) each vector element from (or to) memory. And the summation
reduction operation could also be emulated by just adding all the
vector elements up.
But this would destroy the scalability of a program I designed (on
paper).
I would like to test this program on a real processor, and to maintain
the scalability both features should be O(1) operations.
(I know I am cheating a bit on the reduction operation, that one is
actually O(log N), even in hardware.)
So if some of you could recommend a processor I would be very grateful.
Thanks,
Martijn v/d Horst
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mrkrishnan@gmail.com
Guest
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| Posted:
Fri Dec 17, 2004 1:19 pm Post subject:
Re: Looking for a SIMD DSP |
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Martijn wrote:
| Quote: | I know I could emulate the memory access with stride by just reading
(or writing) each vector element from (or to) memory. And the
summation
reduction operation could also be emulated by just adding all the
vector elements up.
But this would destroy the scalability of a program I designed (on
paper).
|
Without understanding what it meant by "memory access with stride", and
going by the requirements for an SIMD processor, TI C64x qualifies.
C64x is a load/store architecture VLIW processor and can load/store
upto 128 bits per operation.
--
Ramakrishnan |
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Allan Herriman
Guest
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| Posted:
Fri Dec 17, 2004 2:08 pm Post subject:
Re: Looking for a SIMD DSP |
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On 16 Dec 2004 03:03:21 -0800, "Martijn" <martijn.dsp@mailinator.com>
wrote:
| Quote: | Hello,
I am looking for a SIMD or Vector DSP, and I was hoping some of the
people here could recommend one.
The processor I am looking for should support memory accesses with
stride and a summation reduction operation.
So far I found the eLite processor from IBM, but as I understand it, it
is still under development.
Furthermore some old supercomputers like the MasPar MP-1 support the
features that I need, but I would like to find something that fits on a
single chip and is commercially available.
The problem seems to be the memory accesses with stride. I know the
VIRAM supports it, but it lacks the summation reduction operation.
I know I could emulate the memory access with stride by just reading
(or writing) each vector element from (or to) memory. And the summation
reduction operation could also be emulated by just adding all the
vector elements up.
But this would destroy the scalability of a program I designed (on
paper).
I would like to test this program on a real processor, and to maintain
the scalability both features should be O(1) operations.
(I know I am cheating a bit on the reduction operation, that one is
actually O(log N), even in hardware.)
So if some of you could recommend a processor I would be very grateful.
Thanks,
Martijn v/d Horst
|
Is Ray sick or something?
An FPGA could be a suitable platform for massively parallel work like
this. A decent sized FPGA should be able to hold a large parallel
added to perform your summation reduction (I think that's just summing
a column of numbers) to produce 1 result per clock. This might be
practical up to about 200MHz with pipelining (and skill). At these
speeds, the memory bandwidth may be a problem.
"Memory access with stride" sounds like it may not map well to SDRAM
operations. SDRAMs really only achieve good performance when
accessing a bunch of consecutive addresses. Do you need to use SDRAM?
Is your array too big for SRAM? Is it small enough to fit in on-chip
SRAM in an FPGA (e.g. < ~128kbyte)? If so, you could have everything
on chip, and have parallel access to the rams (e.g. ~1000 bit wide
buses), to achieve high performance.
Regards,
Allan |
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Rip
Guest
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| Posted:
Fri Dec 17, 2004 2:25 pm Post subject:
Re: Looking for a SIMD DSP |
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I guess he refers to the ability of elite DSP to access in a SIMD
fashion data thata are not conginous in memory(Disjoint Data). The C64x
or for that matter ant other modern DSP supports SIMD with continous
data only(cause it is the easier way, but are severly affected by
alignment criterions).
If you are looking for a DSP with ability to load disjoint data in SIMD
fashion, I just heard of Elite.
If you are looking with a DSP with auto-pointer modification any modern
DSP will do. |
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Martijn
Guest
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| Posted:
Fri Dec 17, 2004 5:56 pm Post subject:
Re: Looking for a SIMD DSP |
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With "memory access with stride" I mean that I need to access memory
locations that are not adjacent, in a single operation. (The real
problem is that I need data from the same array twice, but I one time
have to read from both adjacent and the other time from non-adjacent
locations, so reorganizing my array is not an option.)
But the SRAM certainly seems an option, I only need a portion of the
array at any one moment, so if I keep that portion in SRAM it should
work out.
The summation reduction is indeed summing a column of numbers, which
can be done with a tree of adders that is O(Log N) deep. I don't know
if it is possible to configure an FPGA in that way, but I'll take a
look at it.
Thanks,
Martijn |
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Martijn
Guest
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| Posted:
Fri Dec 17, 2004 6:00 pm Post subject:
Re: Looking for a SIMD DSP |
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Hi,
Yes, I am looking for the possibility to load disjoint data. So, the
C64x does not seem to be an option.
Thanks,
Martijn |
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Allan Herriman
Guest
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| Posted:
Fri Dec 17, 2004 6:13 pm Post subject:
Re: Looking for a SIMD DSP |
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On 17 Dec 2004 04:56:47 -0800, "Martijn" <martijn.dsp@mailinator.com>
wrote:
| Quote: | With "memory access with stride" I mean that I need to access memory
locations that are not adjacent, in a single operation. (The real
problem is that I need data from the same array twice, but I one time
have to read from both adjacent and the other time from non-adjacent
locations, so reorganizing my array is not an option.)
But the SRAM certainly seems an option, I only need a portion of the
array at any one moment, so if I keep that portion in SRAM it should
work out.
The summation reduction is indeed summing a column of numbers, which
can be done with a tree of adders that is O(Log N) deep. I don't know
if it is possible to configure an FPGA in that way, but I'll take a
look at it.
|
Yes, it is possible to configure an FPGA that way. There may be
limits on N though. Oh, and you probably won't want to use floating
point. I hope your design be expressed in integer or fixed point
arithmetic.
You will also need to pipeline the adder tree. This will still allow
1 result per clock, but the results will be delayed by some clocks.
If you don't have feedback from the output of the adder back to the
input, this delay probably won't matter.
I'm assuming that all inputs to the adder tree are available at the
same time. If they're streaming in from a single ram, then a tree
will give you no performance advantage, since the serial nature of the
ram limits the speed.
How tall are the columns being summed?
Regards,
Allan |
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