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Neil
Guest
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 Posted:
Sat Dec 18, 2004 3:23 am Post subject:
Clock Synchronization |
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I am looking for some material about the various clock synchronization
techniques, their advantages etc.
Thanks
Neil |
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Rene Tschaggelar
Guest
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| Posted:
Sun Dec 19, 2004 9:40 pm Post subject:
Re: Clock Synchronization |
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Neil wrote:
| Quote: | I am looking for some material about the various clock synchronization
techniques, their advantages etc.
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A flipflop does the job. There is little else to be said.
You're not talking about a PLL do you ?
Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net |
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Neil
Guest
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| Posted:
Tue Dec 21, 2004 4:05 am Post subject:
Re: Clock Synchronization |
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Not PLL, I am looking at various types of synchronization techniques
for signals crossing clock boundaries.
- Neil |
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Symon
Guest
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| Posted:
Tue Dec 21, 2004 3:04 pm Post subject:
Re: Clock Synchronization |
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Neil,
Try this http://www.fpga-faq.com/archives/59400.html#59400
Cheers, Syms.
"Neil" <logblog@gmail.com> wrote in message
news:1103583946.091639.312550@c13g2000cwb.googlegroups.com...
| Quote: |
Not PLL, I am looking at various types of synchronization techniques
for signals crossing clock boundaries.
- Neil
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Peter
Guest
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| Posted:
Tue Dec 21, 2004 10:32 pm Post subject:
Re: Clock Synchronization |
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Look at the TechXclusives article
"Moving Data Across Asynchronous Clock Boundaries"
Click at
http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp
and scroll down to 7-10-2001
Peter Alfke |
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Klaus Schleisiek
Guest
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| Posted:
Sat Dec 25, 2004 5:59 pm Post subject:
Re: Clock Synchronization |
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Neil schrieb:
| Quote: | I am looking for some material about the various clock synchronization
techniques, their advantages etc.
|
The following code works pretty reliably, no matter wether the input
pulse is shorter or longer than the output domain clock CLK. On each
input "event", the output produces a pulse one CLK cycle long.
----------------------------------------------------------------
-- metastable safe spike detector
----------------------------------------------------------------
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY spike IS
PORT (reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
i : IN STD_LOGIC;
o : OUT STD_LOGIC);
END spike;
ARCHITECTURE rtl OF spike IS
ATTRIBUTE init : STRING;
SIGNAL hold : STD_LOGIC := '0'; ATTRIBUTE init OF hold : SIGNAL IS "0";
SIGNAL edge_d : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL edge : STD_LOGIC;
SIGNAL edge_set : STD_LOGIC;
BEGIN
o <= edge;
edge_set <= i AND NOT (edge OR hold OR edge_d(1));
async_edge : PROCESS (edge_set, clk)
BEGIN
IF edge_set='1' THEN
edge_d <= "11";
ELSIF rising_edge(clk) THEN
edge_d <= edge_d(0) & '0';
edge <= '0';
IF edge_d="10" THEN
edge <= '1';
END IF;
IF reset='1' THEN
edge_d <= "00";
END IF;
END IF;
END PROCESS async_edge;
pulse_holdoff : PROCESS (edge_set, i)
BEGIN
IF edge_set='1' THEN
hold <= '1';
ELSIF falling_edge(i) THEN
hold <= '0';
END IF;
END PROCESS pulse_holdoff;
END rtl;
Klaus Schleisiek
kschleisiek AT XYfreenet.de
If you want to send me an e-mail, use above address and remove XY |
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Elder Costa
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