| Author |
Message |
Yogesh
Guest
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 Posted:
Sat Dec 18, 2004 1:51 pm Post subject:
DRAM controller policies |
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The current DRAM devices support both open page and close page
policies.Does that mean the memory controller is capable of enabling or
disabling the policies.If that is the case, does the memory controller
keep a track of the row locality and use open page if it is high or use
close page..since the decision of the policy to implement would be a
complex one...the memory controller has to have some mechanism of
keeping the history..there has been no information on how this is
implemented any where..any ideas?
Thanks
Yogesh |
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David Wang
Guest
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| Posted:
Sat Dec 18, 2004 11:32 pm Post subject:
Re: DRAM controller policies |
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Yogesh <yogesh.kinikar@gmail.com> wrote:
| Quote: | Wouldn't it be nice if the policy can be changed dynamically..A recent
publication at the MICRO-37 "Adaptive History Based Memory Schedulers"
has a history of recently scheduled memory operations,this might help
in some way to decide the policy to use..may be..
|
When you design a memory system, you look at what the memory system
is supposed to support. Paging policy is one of the variables, but
it's not an independent variable. It's tied to how the address mapping
scheme of the memory system is set up, and you can't change that
dynamically.
--
davewang202(at)yahoo(dot)com |
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Wes Felter
Guest
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| Posted:
Sun Dec 19, 2004 1:50 am Post subject:
Re: DRAM controller policies |
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On 2004-12-18 02:51:34 -0600, "Yogesh" <yogesh.kinikar@gmail.com> said:
| Quote: | The current DRAM devices support both open page and close page
policies.Does that mean the memory controller is capable of enabling or
disabling the policies.
|
Yes.
| Quote: | If that is the case, does the memory controller
keep a track of the row locality and use open page if it is high or use
close page..since the decision of the policy to implement would be a
complex one...the memory controller has to have some mechanism of
keeping the history..there has been no information on how this is
implemented any where..any ideas?
|
That is possible, but I've never heard of any memory controllers that
implement it. AFAICT, all the systems out there just use open page or
closed page.
--
Wes Felter - wesley@felter.org - http://felter.org/wesley/ |
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Yogesh
Guest
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| Posted:
Sun Dec 19, 2004 3:54 am Post subject:
Re: DRAM controller policies |
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Wouldn't it be nice if the policy can be changed dynamically..A recent
publication at the MICRO-37 "Adaptive History Based Memory Schedulers"
has a history of recently scheduled memory operations,this might help
in some way to decide the policy to use..may be..
Yogesh
Wes Felter wrote:
| Quote: | On 2004-12-18 02:51:34 -0600, "Yogesh" <yogesh.kinikar@gmail.com
said:
The current DRAM devices support both open page and close page
policies.Does that mean the memory controller is capable of
enabling or
disabling the policies.
Yes.
If that is the case, does the memory controller
keep a track of the row locality and use open page if it is high or
use
close page..since the decision of the policy to implement would be
a
complex one...the memory controller has to have some mechanism of
keeping the history..there has been no information on how this is
implemented any where..any ideas?
That is possible, but I've never heard of any memory controllers that
implement it. AFAICT, all the systems out there just use open page or
closed page.
--
Wes Felter - wesley@felter.org - http://felter.org/wesley/ |
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Guest
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| Posted:
Mon Dec 20, 2004 10:55 pm Post subject:
Re: DRAM controller policies |
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"That is possible, but I've never heard of any memory controllers that
implement it. AFAICT, all the systems out there just use open page or
closed page."
This is not actually correct. The Opteron processors use a policy that
is open page for short durations and closed page for longer durations
(between accesses). So, when you have high stream-like traffic, Opteron
acts like an open page policy. When you have large scale random
accesses (like TPC) it operates like a closed page policy. There is
no particular reason that one could not use a policy predictor and
change modes on the fly as the situation changes. |
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Yogesh
Guest
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| Posted:
Tue Dec 21, 2004 4:31 am Post subject:
Re: DRAM controller policies |
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MitchAlsup@aol.com wrote:
| Quote: | "That is possible, but I've never heard of any memory controllers
that
implement it. AFAICT, all the systems out there just use open page or
closed page."
This is not actually correct. The Opteron processors use a policy
that
is open page for short durations and closed page for longer durations
(between accesses). So, when you have high stream-like traffic,
Opteron
acts like an open page policy. When you have large scale random
accesses (like TPC) it operates like a closed page policy. There is
no particular reason that one could not use a policy predictor and
change modes on the fly as the situation changes.
|
Yes I agree...since I have looked at a number of datasheets for DRAM's
there is always one type of address mapping mechanism for both open
page and close page policies...which means address mapping scheme is
not dependent on the controller policies.. |
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David Wang
Guest
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| Posted:
Tue Dec 21, 2004 11:08 am Post subject:
Re: DRAM controller policies |
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Yogesh <yogesh.kinikar@gmail.com> wrote:
| Quote: | MitchAlsup@aol.com wrote:
"That is possible, but I've never heard of any memory controllers
that
implement it. AFAICT, all the systems out there just use open page or
closed page."
This is not actually correct. The Opteron processors use a policy
that
is open page for short durations and closed page for longer durations
(between accesses). So, when you have high stream-like traffic,
Opteron
acts like an open page policy. When you have large scale random
accesses (like TPC) it operates like a closed page policy. There is
no particular reason that one could not use a policy predictor and
change modes on the fly as the situation changes.
Yes I agree...since I have looked at a number of datasheets for DRAM's
there is always one type of address mapping mechanism for both open
page and close page policies...which means address mapping scheme is
not dependent on the controller policies..
|
The mechanism by which physical addresses are mapped to DRAM
addresses cannot be found in any DRAM device datasheets. You
have to look in datasheets for the system (memory) controllers.
You will find that different controllers have different
address mapping mechanisms. If you look into it, you'll
find the correlation between paging policies and (controller)
address mapping schemes.
You can couple any address mapping scheme to any controller
policy you want, but you won't get optimal performance if you
decide that "address mapping scheme doesn't matter and it's
independent of the DRAM paging policy".
--
davewang202(at)yahoo(dot)com |
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