| Author |
Message |
Nick Maclaren
Guest
|
 Posted:
Tue Dec 21, 2004 3:08 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
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In article <rjJxd.14431$uM5.7644@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
| Quote: |
One point is that trying to be all things to all men is hard to get
right, and a second is that you don't need to have different ISAs
to have two simpler designs. The ability to switch the unspecialised
threads also means that you get the efficiency of having a uniform
design.
But if the two types of cores had differences in handling precision of
interrupts, etc. could you switch between the two types arbitrarily? If you
expected precision interrupts, were executing on a core without them and got
one, couldn't that cause problems for you?
|
Not if done right - which should be the motto for most IT.
You would tag threads and not run one that requires precise interrupts
on a core without them. Ditto for fast floating-point (and/or full
IEEE 754 support) or whatever. The majority of threads would need no
tagging, and so could be moved to balance the system.
There is more than one way to kill a cat.
Regards,
Nick Maclaren. |
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 |
Stephen Fuld
Guest
|
| Posted:
Tue Dec 21, 2004 8:37 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cq8sno$s6e$1@gemini.csx.cam.ac.uk...
| Quote: | In article <rjJxd.14431$uM5.7644@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
One point is that trying to be all things to all men is hard to get
right, and a second is that you don't need to have different ISAs
to have two simpler designs. The ability to switch the unspecialised
threads also means that you get the efficiency of having a uniform
design.
But if the two types of cores had differences in handling precision of
interrupts, etc. could you switch between the two types arbitrarily? If
you
expected precision interrupts, were executing on a core without them and
got
one, couldn't that cause problems for you?
Not if done right - which should be the motto for most IT.
You would tag threads and not run one that requires precise interrupts
on a core without them. Ditto for fast floating-point (and/or full
IEEE 754 support) or whatever. The majority of threads would need no
tagging, and so could be moved to balance the system.
|
Tagging of some processes to run on particular cores is precisely what I
suggested previously, but you talked about the advantages of having
uniformity of design, which this proposal doesn't have. It is just a
different degree of difference.
--
- Stephen Fuld
e-mail address disguised to prevent spam |
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Nick Maclaren
Guest
|
| Posted:
Tue Dec 21, 2004 8:55 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
In article <OqXxd.1135591$Gx4.1062070@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|>
|> Tagging of some processes to run on particular cores is precisely what I
|> suggested previously, but you talked about the advantages of having
|> uniformity of design, which this proposal doesn't have. It is just a
|> different degree of difference.
We are at cross-purposes.
If you use the same ISA, then tagging is optional - i.e. it can be
used for performance, but the operating system can override it if
there is a crisis.
If you support variant ISAs in exactly the same way as is done at
present (i.e. privileged versus unprivileged), then tagging comes
essentially for free.
There are many ways to kill this cat.
Regards,
Nick Maclaren. |
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Dan Koren
Guest
|
| Posted:
Tue Dec 21, 2004 10:59 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cq9h11$b9u$1@gemini.csx.cam.ac.uk...
| Quote: |
In article <OqXxd.1135591$Gx4.1062070@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|
|> Tagging of some processes to run on particular cores is precisely what
I
|> suggested previously, but you talked about the advantages of having
|> uniformity of design, which this proposal doesn't have. It is just a
|> different degree of difference.
We are at cross-purposes.
If you use the same ISA, then tagging is optional - i.e. it can be
used for performance, but the operating system can override it if
there is a crisis.
If you support variant ISAs in exactly the same way as is done at
present (i.e. privileged versus unprivileged), then tagging comes
essentially for free.
|
Unfortunately, privileged vs. unprivileged is a
binary solution that would not handle well the
case of multiple resource classes, and is also
tainted with address space implications.
I believe this is an important enough problem
to deserve a clean solution. In a system with
multiple resource classes, each processor (or
processing subsystem) and each thread should
be tagged with a signature of the resources
they provide or require. This could be say,
a 64-bit string. An OS could then adopt one
of two policies: schedule threads only on
processors whose resource signatures match
those required by the thread, or schedule
them on any processor and move them around
when attempting to use resources that are
not provided by the processor they currently
use -- which should result in a trap, etc...
| Quote: |
There are many ways to kill this cat.
|
Please do not kill any cats -- or I
will report you both to the SPCA! ;-)
dk |
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Stephen Fuld
Guest
|
| Posted:
Wed Dec 22, 2004 7:57 am Post subject:
Re: Will multicore CPUs have identical cores? |
|
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"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cq9h11$b9u$1@gemini.csx.cam.ac.uk...
| Quote: |
In article <OqXxd.1135591$Gx4.1062070@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|
|> Tagging of some processes to run on particular cores is precisely what
I
|> suggested previously, but you talked about the advantages of having
|> uniformity of design, which this proposal doesn't have. It is just a
|> different degree of difference.
We are at cross-purposes.
If you use the same ISA, then tagging is optional - i.e. it can be
used for performance, but the operating system can override it if
there is a crisis.
|
Maybe I am missing something here. Aren't you the one who usually rails
against current handling of FP exceptions? Are you willing to accept that a
program you wrote that depends on a particular way such exceptions are
handled (say precisely), is "in a crisis" run on a processor that handles
such cases differently? I didn't think you would, but perhaps I
misinterpreted your earlier posts.
--
- Stephen Fuld
e-mail address disguised to prevent spam |
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|
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Nick Maclaren
Guest
|
| Posted:
Wed Dec 22, 2004 2:51 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
In article <Fk7yd.18856$uM5.13284@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
| Quote: |
If you use the same ISA, then tagging is optional - i.e. it can be
used for performance, but the operating system can override it if
there is a crisis.
Maybe I am missing something here. Aren't you the one who usually rails
against current handling of FP exceptions? Are you willing to accept that a
program you wrote that depends on a particular way such exceptions are
handled (say precisely), is "in a crisis" run on a processor that handles
such cases differently? I didn't think you would, but perhaps I
misinterpreted your earlier posts.
|
Then that is a different ISA. The architecture includes the semantics
as well as the syntax.
Yes, there are even more ways to get it wrong than to get it right :-)
Regards,
Nick Maclaren. |
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|
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Sander Vesik
Guest
|
| Posted:
Wed Dec 22, 2004 8:25 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
Stephen Fuld <s.fuld@pleaseremove.att.net> wrote:
| Quote: |
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cq73uj$79g$1@gemini.csx.cam.ac.uk...
In article <q3Exd.1129653$Gx4.891539@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|
|> > For example, half might be strictly in-order, with really slow
|> > floating-point, graphics and other gizmos, but with support for
|> > access to hardware devices, the specialised and privileged I/O
|> > and other instructions and so on.
|
|> I wonder how much die area one would save by doing this? Is it really
|> significant? ...
I doubt it, but that's not where the gain would be. The real gain
would be that you could abandon perfect interruptability on the
other cores, which could considerably simplify performance (as
usual, depending on a lot of things). And, by supporting only
in-order execution, you make some of the nastier kernel interactions
a LOT simpler.
One point is that trying to be all things to all men is hard to get
right, and a second is that you don't need to have different ISAs
to have two simpler designs. The ability to switch the unspecialised
threads also means that you get the efficiency of having a uniform
design.
But if the two types of cores had differences in handling precision of
interrupts, etc. could you switch between the two types arbitrarily? If you
expected precision interrupts, were executing on a core without them and got
one, couldn't that cause problems for you?
|
Not arbitrarily - you would run parts of the kernel on one set of them
and everything else on the others.
--
Sander
+++ Out of cheese error +++ |
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| Back to top |
|
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Stephen Fuld
Guest
|
| Posted:
Wed Dec 22, 2004 9:36 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cqbg36$g05$1@gemini.csx.cam.ac.uk...
| Quote: | In article <Fk7yd.18856$uM5.13284@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
If you use the same ISA, then tagging is optional - i.e. it can be
used for performance, but the operating system can override it if
there is a crisis.
Maybe I am missing something here. Aren't you the one who usually rails
against current handling of FP exceptions? Are you willing to accept that
a
program you wrote that depends on a particular way such exceptions are
handled (say precisely), is "in a crisis" run on a processor that handles
such cases differently? I didn't think you would, but perhaps I
misinterpreted your earlier posts.
Then that is a different ISA. The architecture includes the semantics
as well as the syntax.
|
But in an earlier post in this thread you proposed a solution with
/on copy
Not necessarily. All the cores could support the same ISA, but
be optimised differently. The following is something I suggested
a long time ago:
For example, half might be strictly in-order, with really slow
floating-point, graphics and other gizmos, but with support for
access to hardware devices, the specialised and privileged I/O
and other instructions and so on. And half might be out-of-order,
with fast floating-point, graphics, but no support for access to
devices.
/off copy
followed by
/on copy
I doubt it, but that's not where the gain would be. The real gain
would be that you could abandon perfect interruptability on the
other cores, which could considerably simplify performance (as
usual, depending on a lot of things). And, by supporting only
in-order execution, you make some of the nastier kernel interactions
a LOT simpler.
/off copy
Those posts seem to say that two cores one with perfect interruptability and
one not have the same ISA. But above you say they would be different. That
is the source of my confusion.
--
- Stephen Fuld
e-mail address disguised to prevent spam |
|
| Back to top |
|
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Nick Maclaren
Guest
|
| Posted:
Wed Dec 22, 2004 9:44 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
In article <Johyd.1142439$Gx4.103619@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|>
|> Those posts seem to say that two cores one with perfect interruptability and
|> one not have the same ISA. But above you say they would be different. That
|> is the source of my confusion.
Sorry - you are correct - I was being seriously unclear.
Most ISA specifications leave the matter of in- and out-of-order
specification to the implementation documents - i.e. it is NOT
part of the ISA as such. It IS, however, part of the implementation
specification. The assumption is that the only code that needs to
worry about that aspect is the deep kernel (scheduler, FLIH etc.)
Let's assume that is true ....
What I meant with the same ISA proposal is that the only threads
that would NECESSARILY be bound are those specialised ones.
It might be worth binding the performance critical application ones
on the cores which would deliver, but they would work (up to the
level of the ISA) on any core.
And most threads couldn't care less.
Regards,
Nick Maclaren. |
|
| Back to top |
|
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Stephen Fuld
Guest
|
| Posted:
Thu Dec 23, 2004 2:21 am Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cqc89r$6je$1@gemini.csx.cam.ac.uk...
| Quote: |
In article <Johyd.1142439$Gx4.103619@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|
|> Those posts seem to say that two cores one with perfect
interruptability and
|> one not have the same ISA. But above you say they would be different.
That
|> is the source of my confusion.
Sorry - you are correct - I was being seriously unclear.
Most ISA specifications leave the matter of in- and out-of-order
specification to the implementation documents - i.e. it is NOT
part of the ISA as such. It IS, however, part of the implementation
specification. The assumption is that the only code that needs to
worry about that aspect is the deep kernel (scheduler, FLIH etc.)
Let's assume that is true ....
What I meant with the same ISA proposal is that the only threads
that would NECESSARILY be bound are those specialised ones.
It might be worth binding the performance critical application ones
on the cores which would deliver, but they would work (up to the
level of the ISA) on any core.
And most threads couldn't care less.
|
Yes. Now we are back to the idea of having multiple thread "types" tagged
in some way whether they care which core the execute on or not. In the one
case you proposed, the issue is precise interruptability. In the case I
proposed, it is the need for floating point/fancy graphics instructions at
all. I maintain that is a matter of degree of difference, not thether there
is a difference or not. Clearly a core with "slow" FP/graphics can execute
more thread types than one with out these instructions, but it would be
larger so you could fit fewer of them on the same die. Which is the right
choice? I suspect that, as with most things, it depends upon workload.
Perhaps even all three types on a die makes sense???
--
- Stephen Fuld
e-mail address disguised to prevent spam |
|
| Back to top |
|
|
Stephen Fuld
Guest
|
| Posted:
Thu Dec 23, 2004 2:21 am Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Sander Vesik" <sander@haldjas.folklore.ee> wrote in message
news:1103747119.796784@haldjas.folklore.ee...
| Quote: | Stephen Fuld <s.fuld@pleaseremove.att.net> wrote:
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cq73uj$79g$1@gemini.csx.cam.ac.uk...
In article
q3Exd.1129653$Gx4.891539@bgtnsc04-news.ops.worldnet.att.net>,
"Stephen Fuld" <s.fuld@PleaseRemove.att.net> writes:
|
|> > For example, half might be strictly in-order, with really slow
|> > floating-point, graphics and other gizmos, but with support for
|> > access to hardware devices, the specialised and privileged I/O
|> > and other instructions and so on.
|
|> I wonder how much die area one would save by doing this? Is it
really
|> significant? ...
I doubt it, but that's not where the gain would be. The real gain
would be that you could abandon perfect interruptability on the
other cores, which could considerably simplify performance (as
usual, depending on a lot of things). And, by supporting only
in-order execution, you make some of the nastier kernel interactions
a LOT simpler.
One point is that trying to be all things to all men is hard to get
right, and a second is that you don't need to have different ISAs
to have two simpler designs. The ability to switch the unspecialised
threads also means that you get the efficiency of having a uniform
design.
But if the two types of cores had differences in handling precision of
interrupts, etc. could you switch between the two types arbitrarily? If
you
expected precision interrupts, were executing on a core without them and
got
one, couldn't that cause problems for you?
Not arbitrarily - you would run parts of the kernel on one set of them
and everything else on the others.
|
Sure. But if you were going to do that, the "kernel" cores wouldn't need
floating point nor fancy graphics instructions at all, and we are back to my
original proposal.
--
- Stephen Fuld
e-mail address disguised to prevent spam |
|
| Back to top |
|
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Nick Maclaren
Guest
|
| Posted:
Thu Dec 23, 2004 2:35 am Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
In article <4zlyd.21129$uM5.16487@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
| Quote: |
Yes. Now we are back to the idea of having multiple thread "types" tagged
in some way whether they care which core the execute on or not. In the one
case you proposed, the issue is precise interruptability. In the case I
proposed, it is the need for floating point/fancy graphics instructions at
all. I maintain that is a matter of degree of difference, not thether there
is a difference or not. Clearly a core with "slow" FP/graphics can execute
more thread types than one with out these instructions, but it would be
larger so you could fit fewer of them on the same die. Which is the right
choice? I suspect that, as with most things, it depends upon workload.
Perhaps even all three types on a die makes sense???
|
Possibly. I suspect that the sweet spot is two, because the really
incompatible aspects are the scheduler/FLIH need for instruction-
level precision and the HPC application need for serious out-of-order
execution.
And most threads don't really care, which is useful.
Regards,
Nick Maclaren. |
|
| Back to top |
|
|
Stephen Fuld
Guest
|
| Posted:
Thu Dec 23, 2004 7:58 am Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cqcpac$afh$1@gemini.csx.cam.ac.uk...
| Quote: | In article <4zlyd.21129$uM5.16487@bgtnsc05-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
Yes. Now we are back to the idea of having multiple thread "types" tagged
in some way whether they care which core the execute on or not. In the
one
case you proposed, the issue is precise interruptability. In the case I
proposed, it is the need for floating point/fancy graphics instructions at
all. I maintain that is a matter of degree of difference, not thether
there
is a difference or not. Clearly a core with "slow" FP/graphics can
execute
more thread types than one with out these instructions, but it would be
larger so you could fit fewer of them on the same die. Which is the right
choice? I suspect that, as with most things, it depends upon workload.
Perhaps even all three types on a die makes sense???
Possibly. I suspect that the sweet spot is two, because the really
incompatible aspects are the scheduler/FLIH need for instruction-
level precision and the HPC application need for serious out-of-order
execution.
And most threads don't really care, which is useful.
|
Yes. But outside of your world (HPC), I wonder what percentage of threads
require any FP/graphics stuff. I suspect it is a minority. I could see a
chip designed for say a database server, with a few FP capable cores and a
lot more non-fp capable cores.
--
- Stephen Fuld
e-mail address disguised to prevent spam |
|
| Back to top |
|
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Nick Maclaren
Guest
|
| Posted:
Thu Dec 23, 2004 3:00 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
In article <IAsyd.1145654$Gx4.570071@bgtnsc04-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
| Quote: |
Yes. But outside of your world (HPC), I wonder what percentage of threads
require any FP/graphics stuff. I suspect it is a minority. I could see a
chip designed for say a database server, with a few FP capable cores and a
lot more non-fp capable cores.
|
Nowadays, almost all - it is often used in libraries and for other
purposes where it avoids the need for complicated fixed-point code.
It doesn't matter if it is (well) emulated or otherwise slow.
Regards,
Nick Maclaren. |
|
| Back to top |
|
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Stephen Fuld
Guest
|
| Posted:
Thu Dec 23, 2004 10:38 pm Post subject:
Re: Will multicore CPUs have identical cores? |
|
|
"Nick Maclaren" <nmm1@cus.cam.ac.uk> wrote in message
news:cqe4vm$4up$1@gemini.csx.cam.ac.uk...
| Quote: | In article <IAsyd.1145654$Gx4.570071@bgtnsc04-news.ops.worldnet.att.net>,
Stephen Fuld <s.fuld@PleaseRemove.att.net> wrote:
Yes. But outside of your world (HPC), I wonder what percentage of threads
require any FP/graphics stuff. I suspect it is a minority. I could see a
chip designed for say a database server, with a few FP capable cores and a
lot more non-fp capable cores.
Nowadays, almost all - it is often used in libraries and for other
purposes where it avoids the need for complicated fixed-point code.
|
Wow, I'm surprised. Can you give some examples of common routines that
coulde be expected to be used by most threads that use FP and for what
specific purpose?
--
- Stephen Fuld
e-mail address disguised to prevent spam |
|
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|
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