| Author |
Message |
Antti Lukats
Guest
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 Posted:
Mon Dec 20, 2004 11:18 pm Post subject:
edk-chipscope 6.2 to 6.3 update |
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1) EDK 6.3 seems to have introduced a new SW bug, if the "global
pointer optimization" is checked irratic behaviour happens. This is
what caused problems to Rudolf Usselman (at least I think so)
2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope
service pack!! and not for Spartan II-E, but only for newer families!
well good thing of course in any case
Antti |
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Symon
Guest
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| Posted:
Mon Dec 20, 2004 11:36 pm Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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Except that it's not good enough. The storage qualifier should be a clock
enable for the whole unit. Otherwise, P&R can stop because it's impossible
to meet the clock timing recommendations, even though it'd be OK if the
qualification was done with an enable. When you select a clock for the ILA,
you should also be able to select an enable to associate with that clock.
The enable should connect to the CE pins of all the storage devices. You can
use an AND gate for the WE on the SRLUTs, I suppose. C'mon Xilinx, FIX IT!
Or release the HDL for ChipScope so we can fix it for you. Don't make me
reverse engineer it! ;-)
Cheers, Syms.
"Antti Lukats" <avrbasic@hotmail.com> wrote in message
news:34d005c8.0412201018.5e57a75a@posting.google.com...
| Quote: | 2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope
service pack!! and not for Spartan II-E, but only for newer families!
well good thing of course in any case
Antti |
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Vasanth Asokan
Guest
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| Posted:
Tue Dec 21, 2004 12:56 am Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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| Quote: | 1) EDK 6.3 seems to have introduced a new SW bug, if the "global
pointer optimization" is checked irratic behaviour happens. This is
what caused problems to Rudolf Usselman (at least I think so)
|
Please try SP2 when its out. This is fixed in the service pack. |
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Bob Perlman
Guest
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| Posted:
Tue Dec 21, 2004 1:20 am Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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On Mon, 20 Dec 2004 10:36:56 -0800, "Symon" <symon_brewer@hotmail.com>
wrote:
| Quote: | Except that it's not good enough. The storage qualifier should be a clock
enable for the whole unit. Otherwise, P&R can stop because it's impossible
to meet the clock timing recommendations, even though it'd be OK if the
qualification was done with an enable. When you select a clock for the ILA,
you should also be able to select an enable to associate with that clock.
The enable should connect to the CE pins of all the storage devices. You can
use an AND gate for the WE on the SRLUTs, I suppose. C'mon Xilinx, FIX IT!
Or release the HDL for ChipScope so we can fix it for you. Don't make me
reverse engineer it! ;-)
Cheers, Syms.
|
Yes! I agree 470%! (My approval percentages are arrived at with the
same methods FPGA manufacturers use to come up with gate counts.)
Bob Perlman
Cambrian Design Works
| Quote: | "Antti Lukats" <avrbasic@hotmail.com> wrote in message
news:34d005c8.0412201018.5e57a75a@posting.google.com...
2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope
service pack!! and not for Spartan II-E, but only for newer families!
well good thing of course in any case
Antti
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Matthew Ouellette
Guest
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| Posted:
Tue Dec 21, 2004 2:35 am Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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Antti,
Antti Lukats wrote:
| Quote: | 1) EDK 6.3 seems to have introduced a new SW bug, if the "global
pointer optimization" is checked irratic behaviour happens. This is
what caused problems to Rudolf Usselman (at least I think so)
|
Could you please open a case with our technical support hotline in
regards to this issue and provide an
example for the hotline engineer?
Matt
| Quote: |
2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope
service pack!! and not for Spartan II-E, but only for newer families!
well good thing of course in any case
Antti |
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Rudolf Usselmann
Guest
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| Posted:
Wed Dec 22, 2004 7:59 am Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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Vasanth Asokan wrote:
| Quote: |
1) EDK 6.3 seems to have introduced a new SW bug, if the "global
pointer optimization" is checked irratic behaviour happens. This is
what caused problems to Rudolf Usselman (at least I think so)
Please try SP2 when its out. This is fixed in the service pack.
|
Actually I think I use SP2 (EDK 6.3.1) and am still having
the problem.
Best Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis |
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avrbasic
Guest
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| Posted:
Sat Dec 25, 2004 8:53 pm Post subject:
Re: edk-chipscope 6.2 to 6.3 update |
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|
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
news:vuces0ppfo7jake9u20r25um83r24ebutn@4ax.com...
| Quote: | On Mon, 20 Dec 2004 10:36:56 -0800, "Symon" <symon_brewer@hotmail.com
wrote:
Except that it's not good enough. The storage qualifier should be a clock
enable for the whole unit. Otherwise, P&R can stop because it's
impossible
to meet the clock timing recommendations, even though it'd be OK if the
qualification was done with an enable. When you select a clock for the
ILA,
you should also be able to select an enable to associate with that clock.
The enable should connect to the CE pins of all the storage devices. You
can
use an AND gate for the WE on the SRLUTs, I suppose. C'mon Xilinx, FIX
IT!
Or release the HDL for ChipScope so we can fix it for you. Don't make me
reverse engineer it! ;-)
Cheers, Syms.
Yes! I agree 470%! (My approval percentages are arrived at with the
same methods FPGA manufacturers use to come up with gate counts.)
Bob Perlman
Cambrian Design Works
|
The storage qualifier is defenetly useful for some cases. But yes a more
open OnChip Instrumentation would be nice. But It looks like none of the
FPGA vendors is interested in it :(
RE of ChipScope isnt so complex but it doesnt make much sense, it would
better to design from ground up!
ChipScope ICON is actually a JTAG "Hub" that creates 15 virtual JTAG chains
with 2 pairs of 16 update signals per port.
control[35:0] actually is
TDI
TDO
TCK
update_lo[15:0]
update_hi[15:0]
update_lo[0] is used by all cores as enable for Serial ROM that includes the
core ID and parameters. This serial ROM is scanned when Chipscope analyzer
connects.
Altium Livedesign uses different approuch: for each core separate JTAG TAP
instance is added, all those are added into secondary "soft" JTAG chain that
is controlled over modified Xilinx Cable III where additional pins are
allocated to the secondary soft chain.
Altera SignalTap is I think more similar to ChipScope where "hub" is added
the FPGA intgernal TAP access primitive.
I do have some simple IP cores (in verilog) that can be connected to ICON
and controlled by ChipScope analyzer, some JAM scripts that can work with
ChipScope cores and some Windows application that also can trigger and read
from ILA core.
please email me in private in case of interest.
Antti Lukats |
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