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praveen · Guest

Shreyas,

Go through the book
PCI SYSTEM ARCHITECTURE by TOM SHANLEY / DON ANDERSON

Very good book....you will understand the whole PCI architecture.

Regards
Praveen

Shreyas Kulkarni · Guest

the thing that created this mess of mis-understanding is the fact that
- nearly all the pci cards that an end-user like me uses, are target
only devices. (there is another category called bus-maters, which i was
unaware of.)

so naturally i thought - if all devices are targets then the master
must be the arbitar; and as it initiates the transaction, i could call
it as an initiator!

the right thing is (plz verify) -
1. nearly all devices are target-only.
2. bus-maters are also pci cards that can initiate transaction.
3. usually the cpu itself is the bus master or simply the master.
4. the arbiter controls these targets and masters.

so in short (in general) -
target-only pci card = slave
cpu = master
arbiter = controller

i think i have put it right this time!
(have i really ? ;-) )
anyway, thanks for all the replies and help.

regards,
Shreyas Kulkarni

Vitus · Guest

Shreyas Kulkarni · Guest

i was told that the cards that have bus-mastering support have the same
mentioned as a feature in their manuals. as far as i m concerned, i
haven't come across any card that has this type of feature listed,
except that i have read somewhere that some scsi cards have
bus-mastering capability.

that's why i think many of the pci devices are target only.

will somebody shed some light on this ?

also, if that is wrong, then will somebody plz mention currently
available bus-master devices which are used by end-users?

Shreyas Kulkarni · Guest

i was told that the cards that have bus-mastering support have the same
mentioned as a feature in their manuals. as far as i m concerned, i
haven't come across any card that has this type of feature listed,
except that i have read somewhere that some scsi cards have
bus-mastering capability.

that's why i think many of the pci devices are target only.

will somebody shed some light on this ?

also, if that is wrong, then will somebody plz mention currently
available bus-master devices which are used by end-users?

Guest · Posted: Sat Dec 25, 2004 6:36 am Post subject: Re: PCI doubt

Before ethernet was embedded in the chipset, NICs were PCI cards. The
good ones were PCI bus masters. That's one example. Others include
bridges and modems. Any application that would prefer to move data
without bothering the CPU (that is, DMA) could be a master.

Target devices are generally more prevalent in the PC but PCI is used
for much more than a system 'local bus'.
http://www.osronline.com/lists_archive/ntdev/thread2488.html

Purvesh · Guest

Hi All,
I have been designing PCI/PCI-X cores for many many years - here is
small note on masters/initiators/targets/arbiters/completors etc.

PCI
===

Masters:
------------
Masters are the devices that have capability of starting the
transaction on the bus. They control how long the transaction remains
active unless pre-empted by other masters(with the helpof arbiter) or
premature transaction termination occurs.

Slaves or Targets:
--------------------------

These are the devices that respond to transactions initiated by master.
They have ability to break the transaction pre-maturely.

Arbiters
-----------:

Since PCI is a bused based system, there could be numerous masters on
the same bus which could be asking for bus resource, hence you need an
arbiter which determines which master can access the bus (based on
internal algorithm not defined in spec). Generally arbiters are on
system mother boards in a chip called central resource. However for
embedded systems, the arbiter can reside on any one of the master. Also
lots of cpu have built in pci arbiter. You can have only one arbiter
per bus unless distributed arbitration schema is designed for (very
hard).

PCI-X
=====

Initiators
------------

Initiators are similar to masters of PCI.

Completors
-----------------

Completors are similar to targets of PCI with added capability of
becoming bus master to complete a pending split transaction. Split
transactions are normal transactions started by initiator, but
completor realises that it cannot complete the transaction at that
particular time so tells master to back off and says when it has read
data available, it will become bus master and provide initiator with
the data. Note only read transactions can be split by completor and
initiator cannot re-split the split completion transaction.

for a system you need both masters/initiators as well
slaves/completors.
Hope this clears some air. If not send me personal email.

-Purvesh

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