| Author |
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JTW
Guest
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 Posted:
Tue Dec 21, 2004 11:23 pm Post subject:
Memory Controller |
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| If I have two or more sections of logic in my FPGA that need to read and write to the same memory, what is the typical/standard approach to control who writes/reads when? Is there an example somewhere that I could look at? Thanks, JTW |
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Sandeep Kulkarni
Guest
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| Posted:
Tue Dec 21, 2004 11:23 pm Post subject:
Re: Memory Controller |
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Hello,
To keep it simple you can try using a dual port ram.
Xilinx advantage true dual port ram.
Sandeep
"Tommy Thorn" <foobar@nowhere.void> wrote in message
news:uj8yd.13718$_3.154971@typhoon.sonic.net...
| Quote: | JTW wrote:
If I have two or more sections of logic in my FPGA that need to read and
write
to the same memory, what is the typical/standard approach to control
who
writes/reads when? Is there an example somewhere that I
could look at?
Thanks, JTW
It's a problem more general than just memory, ie. you could be sharing
other devices. For the most general case you need some kind of
interconnect structure and arbitration, like for example Avalon (offered
by Altera) or WISHBONE (notably used by OpenCores, though I couldn't
seem find a bus arbiter).
Often however, you can use system specific knowledge to adopt a simpler
solution, such as running the memory at twice the speed, using odd
cycles for one device, and even for the other (rarely works for external
memory though).
Tommy |
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Tommy Thorn
Guest
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| Posted:
Wed Dec 22, 2004 7:59 am Post subject:
Re: Memory Controller |
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JTW wrote:
| Quote: | If I have two or more sections of logic in my FPGA that need to read and write
to the same memory, what is the typical/standard approach to control who
writes/reads when? Is there an example somewhere that I
could look at?
Thanks, JTW
|
It's a problem more general than just memory, ie. you could be sharing
other devices. For the most general case you need some kind of
interconnect structure and arbitration, like for example Avalon (offered
by Altera) or WISHBONE (notably used by OpenCores, though I couldn't
seem find a bus arbiter).
Often however, you can use system specific knowledge to adopt a simpler
solution, such as running the memory at twice the speed, using odd
cycles for one device, and even for the other (rarely works for external
memory though).
Tommy |
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