fwj_733
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 Posted:
Fri Dec 24, 2004 2:08 pm Post subject:
Timing simulation : BRAM simulation proble |
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I use a blockram in my FPGA design, when I use ISE5.2 generate the post simulation, and use Model sim SE 5.6 to simulate, it works well. But when upgrade to ISE6.2, cause a lot of problem. Model sim issue a lot of such warnings:
* Warning: /X_RAMB4_S16 HOLD High VIOLATION ON ADDR(2) WITH RESPECT TO CLK; # Expected := 352578022931546.37 ns; Observed := 7.894 ns; At : 11.564 ns # Time: 11564 ps Iteration: 1 Instance: /synth_demux_synth_tb_vhd_tb/uut/fir_i_b6096 Time: 1095432 ps Iteration: 1 Instance: /synth_demux_synth_tb_vhd_tb/uut/fir_i_b6096 # ** Warning: /X_RAMB4_S16 HOLD High VIOLATION ON DI(3) WITH RESPECT TO CLK; # Expected := 352578950644482.37 ns; Observed := 11.919 ns; At : 1095.589 ns The warning is very confusing: how can I expect it valid after 352578950644482.37 ns? The BlockRam output all turned to "X". I check the SDF file generated by ISE 6.2, it's setup and hold time is(SETUPHOLD (posedge DI[4]) (posedge CLK) (1042:1042:1042) (0:0:0))(4135:4135:4135)). I think, holdd expected time should be holdhigh or holdlow. Model sim must have calcualte wrong, but as it work well for ISE5.2, seems it has sth to do with ISE6.2. Could any one provide help? thank you all. Best regards. |
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