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Michel Bieleveld
Guest
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 Posted:
Tue Jan 04, 2005 1:55 am Post subject:
Skew between signals |
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The problem is that i have two output signals, CE and WE, now i want
to "schedule" the rising of WE just after the rising of CE.
I tried it by putting the rising statement of CE earlier in the
process than the rising of WE, unfortunately, but expectly, without
any succes.
So how can i "schedule" the rising of the signal after the other. I
don`t want to do doubling of the clock, using both clock edges, etc. I
hope to do it with just constraints in Xilinx ISE.
So can anyone tell me how to fix this problem, any info would be
appreciated !
Michel Bieleveld. |
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Falk Brunner
Guest
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| Posted:
Tue Jan 04, 2005 2:02 am Post subject:
Re: Skew between signals |
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"Michel Bieleveld" <aktaeon@gmail.com> schrieb im Newsbeitrag
news:47fe273e.0501031255.4e19d7fc@posting.google.com...
| Quote: | The problem is that i have two output signals, CE and WE, now i want
to "schedule" the rising of WE just after the rising of CE.
I tried it by putting the rising statement of CE earlier in the
process than the rising of WE, unfortunately, but expectly, without
any succes.
|
Sure, we are talking about real world, synthesizable HDL. The delay
statements in VHDL are for simulation only.
VHDL is concurrent, statements are processed in parallel as fast as possible
(given by the target technology).
| Quote: | So how can i "schedule" the rising of the signal after the other. I
don`t want to do doubling of the clock, using both clock edges, etc. I
hope to do it with just constraints in Xilinx ISE.
|
Hope is good, but basic understading of things is better.
So how do you think such a thing might be possible.?? Adding a RC-Filter to
an IO?
There are serval tricks to get a more or less usefull workaround, but a
reliable and safe way is to use a clock (and maybe the inverted edge).
Nothing wrong with this.
You can "adjust" the phase relation also by setting the IO driver to
different driving strength and slew rates, but this is IMHO not a clean way
(phase will vary with VCC and temperature)
Regrads
Falk |
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Eric
Guest
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| Posted:
Tue Jan 04, 2005 3:53 am Post subject:
Re: Skew between signals |
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if you want WE to toggle after CE you have two states not one (If you
think of your design as a state machine). So doubling the clk is the
best solution. That way you'll have WE toggle on one clk edge and CE
toggle on the next.
It's not the answer you wanted to hear, but i think it is the way that
will get you the most consistant results.
Eric |
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Purvesh
Guest
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| Posted:
Tue Jan 04, 2005 5:51 am Post subject:
Re: Skew between signals |
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What Eric is suggesting is the cleanest way to do things.
Another alternative without going thru re designing logic too much is
to use DCM to generate half frequency clk phase shifted by what ever
delay you want. Use that clock as a gate to your WE. This will cause
bad output times on you WE and could be a concern if you are planning
to run at very high speeds and there is no margin to play with (if
board delay plus set up times plus clk to q are barely meeting).
Else if you are generating WE thru a flop, things are still easier. Use
DCM to generate same frequency clk as your core clk, delay phase shift
by whatever amount you want and use that to clock your WE.
Hope all these help,
Regards,
Purvesh
Eric wrote:
| Quote: | if you want WE to toggle after CE you have two states not one (If you
think of your design as a state machine). So doubling the clk is the
best solution. That way you'll have WE toggle on one clk edge and CE
toggle on the next.
It's not the answer you wanted to hear, but i think it is the way
that
will get you the most consistant results.
Eric |
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Jeff Cunningham
Guest
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| Posted:
Tue Jan 04, 2005 6:38 pm Post subject:
Re: Skew between signals |
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Michel Bieleveld wrote:
| Quote: | The problem is that i have two output signals, CE and WE, now i want
to "schedule" the rising of WE just after the rising of CE.
|
You could make the CE signal bidirectional and use the fed back signal
from the CE pin to gate the trailing edge of the WE signal.
WE out: std_logic;
CE inout: std_logic;
CE <= internal_CE
WE <= internal_WE and CE; -- assuming both are active high.
You might need some other logic to disable this gating function at the
leading edge if WE leading edge must come before CE leading edge. Also,
you must make sure the internal WE signal lasts longer than the internal
CE signal so that skew between the two signals does not cause the
internal WE to negate before the fed back CE cuts it off.
-Jeff |
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Michel Bieleveld
Guest
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| Posted:
Wed Jan 05, 2005 6:29 pm Post subject:
Re: Skew between signals |
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Thanks for the suggestions !
I am using a spartan 2E so i guess that DCM is not an option for me.
Currently, which also works, I am using an area constraint to put the
logic closer to one pin than the other. In this way everything is
"schedules" as i want to. I was hoping for a similiar and cleaner
result by using some kind of timing constraint.
I imagine that this constraint would accept a minimum of delay
compared to another signal. If this delay after synthesis is not met i
would expect that aditional logic is place between pad and signal to
delay the logic.
Thanks all for your input !
With regards,
Michel Bieleveld. |
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Falk Brunner
Guest
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| Posted:
Wed Jan 05, 2005 11:52 pm Post subject:
Re: Skew between signals |
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"Michel Bieleveld" <thechatter@hotmail.com> schrieb im Newsbeitrag
news:0tqnt0dvs2d1mbgvfv9r0iqkgpboal6gdv@4ax.com...
| Quote: | Thanks for the suggestions !
I am using a spartan 2E so i guess that DCM is not an option for me.
|
The spartan-IIE has the DLL, which can do phase shifts of 90, 180, 270
degree (provided that the clock frequency is >25 MHz)
You can use a 90 degree phase shifted clock to fix the delay in a reliable
way.
| Quote: | Currently, which also works, I am using an area constraint to put the
logic closer to one pin than the other. In this way everything is
"schedules" as i want to. I was hoping for a similiar and cleaner
result by using some kind of timing constraint.
I imagine that this constraint would accept a minimum of delay
compared to another signal. If this delay after synthesis is not met i
would expect that aditional logic is place between pad and signal to
delay the logic.
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Forget about such crap. This was a nasty (but often working) trick in the
good ole, TTL days. No real option anymore.
Regards
Falk |
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