| Author |
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David Kanter
Guest
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 Posted:
Wed Jul 27, 2005 8:15 am Post subject:
Cache coherency protocols: Write-update versus write-invalid |
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Does anyone know of commercial systems that used write-update policies,
rather than write invalidate to maintain cache coherency?
It has been pretty well demonstrated that write-update is a horrible
idea when you want to obtain high performance and you have limited
inter-CPU bandwidth (and even with infinite bandwidth it can lead to
performance losses). However, I could see write-update having some
advantages for samll (2P) multiple CPU embedded systems where reducing
the variation in cache access times would be good (I believe you should
be able to eliminate coherency misses).
Unfortunately, I am too young to have observed any of the older systems
which may have used write-update. If some of the veterans around here
could pipe up on the subject, I'd certainly appreciate it.
Thanks,
David Kanter |
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Del Cecchi
Guest
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| Posted:
Thu Jul 28, 2005 7:52 am Post subject:
Re: Cache coherency protocols: Write-update versus write-inv |
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David Kanter wrote:
| Quote: | Does anyone know of commercial systems that used write-update policies,
rather than write invalidate to maintain cache coherency?
It has been pretty well demonstrated that write-update is a horrible
idea when you want to obtain high performance and you have limited
inter-CPU bandwidth (and even with infinite bandwidth it can lead to
performance losses). However, I could see write-update having some
advantages for samll (2P) multiple CPU embedded systems where reducing
the variation in cache access times would be good (I believe you should
be able to eliminate coherency misses).
Unfortunately, I am too young to have observed any of the older systems
which may have used write-update. If some of the veterans around here
could pipe up on the subject, I'd certainly appreciate it.
Thanks,
David Kanter
Have you looked at DASH and SCI? Those are the two oldest that I am |
aware of.
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.” |
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Anne & Lynn Wheeler
Guest
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| Posted:
Thu Jul 28, 2005 9:17 pm Post subject:
Re: Cache coherency protocols: Write-update versus write-inv |
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Del Cecchi <cecchinospam@us.ibm.com> writes:
| Quote: | Have you looked at DASH and SCI? Those are the two oldest that I am
aware of.
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sci defined 64 "ports" for its shared memory bus implemenation.
convex used two (hp risc) processor boards with sci for 128processor
exemplar.
both dg and sequent used four (intel) processor boards with sci for
256processor systems (sequent was subsequently bought by ibm)
dash was research program at stanford .. the dash project web pages at
stanford have gone 404 (but search engines turn up a lot of dash
references)
and replaced by the flash follow-on
http://www-flash.stanford.edu/
sci was standards effort pushed by slac
http://www.scizzl.com/
there was some concurrent competition between sci and fcs at the time
.... both were using pairs of uni-directional serial fiber optic
(simulating full-dupliex) ... and both were doing definitions for
taking syncronous scsi bus commands and encapsulating as asyncronous
messages.
and fcs was standards effort pushed by llnl
--
Anne & Lynn Wheeler | http://www.garlic.com/~lynn/ |
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Petter Gustad
Guest
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| Posted:
Tue Aug 02, 2005 12:15 am Post subject:
Re: Cache coherency protocols: Write-update versus write-inv |
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Anne & Lynn Wheeler <lynn@garlic.com> writes:
| Quote: | Del Cecchi <cecchinospam@us.ibm.com> writes:
Have you looked at DASH and SCI? Those are the two oldest that I am
aware of.
sci defined 64 "ports" for its shared memory bus implemenation.
|
SCI defines up to 64k nodes for a shared memory interconnect.
| Quote: | there was some concurrent competition between sci and fcs at the time
... both were using pairs of uni-directional serial fiber optic
|
The SCI spec (IEEE-1596) defines a serial coding scheme, however most
implementations used the the 18-bit parallel interface (16-bit data, 1
flag, 1 clock) over copper.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail? |
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