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Paminu
Guest
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 Posted:
Tue Aug 02, 2005 12:15 am Post subject:
My first 1-bit FullAdder |
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I have tried to draw a fullAdder made up only by AND, OR and NOT gates. It
seems to be working fine, but I would like to know for sure. If you have
some time please check it out at:
http://bigblop.blogspot.com/
Any comments appriciated! |
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Tommy Thorn
Guest
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| Posted:
Tue Aug 02, 2005 8:15 am Post subject:
Re: My first 1-bit FullAdder |
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Paminu wrote:
| Quote: | I have tried to draw a fullAdder made up only by AND, OR and NOT gates. It
seems to be working fine, but I would like to know for sure. If you have
some time please check it out at:
http://bigblop.blogspot.com/
Any comments appriciated!
|
It's a wonderful fact of functions over finite domains that you can
"prove" them correct by inspection, simply enumerating the domain and
checking the range. Did you do that?
Just from glancing at your circuit, it looks correct. But is it good?
That really depends on your metric.
You could trivially share some of the inverters, but to truely optimize
the design you have to specify the constraints: how many are you
building? What are your building blocks? (relays, tubes, transistors,
discrete 74X TTL chips, FPGA, ASIC, LEGO, ..?).
BTW, this is not really appropriate for comp.arch.
Tommy |
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Paminu
Guest
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| Posted:
Tue Aug 02, 2005 3:34 pm Post subject:
Re: My first 1-bit FullAdder |
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Tommy Thorn wrote:
| Quote: | Paminu wrote:
I have tried to draw a fullAdder made up only by AND, OR and NOT gates.
It seems to be working fine, but I would like to know for sure. If you
have some time please check it out at:
http://bigblop.blogspot.com/
Any comments appriciated!
It's a wonderful fact of functions over finite domains that you can
"prove" them correct by inspection, simply enumerating the domain and
checking the range. Did you do that?
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Yes but would also like to get some feedback regarding to optimization etc.
| Quote: | Just from glancing at your circuit, it looks correct. But is it good?
That really depends on your metric.
You could trivially share some of the inverters, but to truely optimize
the design you have to specify the constraints: how many are you
building? What are your building blocks? (relays, tubes, transistors,
discrete 74X TTL chips, FPGA, ASIC, LEGO, ..?).
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I need to integrate it into an ALU that has to have a variable bit size. But
I am also looking at the carry-lookahead.
| Quote: | BTW, this is not really appropriate for comp.arch.
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Ok, I took a course in computer architecture where we had to use Gates to
design a CPU (designing/implementing an ALU that contains an Adder) so if
this is not the right group for these questions is there another group that
is more appropriate, because it seems to me that this would be a group
dealing with these type of questions. |
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