Peter \"Firefly\" Lund
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 Posted:
Sat Aug 06, 2005 4:15 pm Post subject:
HPS influence on internal VAX discussions at DEC? |
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Thanks to the recent threads on the VAX, a pleasant change from the
threads on the (*drool*) Alpha, I had another go at the literature.
For some reason I had totally overlooked the papers on HPS
("High-Performance Substrate") by Yale Patt et al until now...
.... all I can say now that I've looked at them is: Wauv! They are
fantastic!
On the one hand, I know there were lots of connections between these guys
and Digital -- on the other hand, their research did not seem to have much
of an impact until the nineties (Intel P6 - whether the Yale Patt ->
Wen-mei Hwu -> Andy Glew connection played a role there, I don't know).
Does anybody know how much the HPS research was discussed internally at
DEC?
How many gates would it take to produce an HPS-like implementation of the
VAX?
-Peter |
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Anton Ertl
Guest
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| Posted:
Sat Aug 06, 2005 10:45 pm Post subject:
Re: HPS influence on internal VAX discussions at DEC? |
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"Peter \"Firefly\" Lund" <firefly@diku.dk> writes:
| Quote: | Thanks to the recent threads on the VAX, a pleasant change from the
threads on the (*drool*) Alpha, I had another go at the literature.
For some reason I had totally overlooked the papers on HPS
("High-Performance Substrate") by Yale Patt et al until now...
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BTW, it's easy to remember the authors because they also have these
initials: Hwu, Patt, Shebanow.
That's the research that I meant when I wrote that "OoO execution with
precise exceptions was just research papers at the time".
Here are some references:
@InProceedings{patt+85a,
author = "Yale N. Patt and {Wen-mei} Hwu and Michael Shebanow",
title = "{HPS}, a New Microarchitecture: Rationale and Introduction",
crossref = "micro85",
pages = "103--108",
annote = "CISC instructions are decoded into RISC instructions,
which are executed in parallel using dynamic
scheduling etc. This microengine is presented as a
restricted data flow machine."
}
@InProceedings{patt+85b,
author = "Yale N. Patt and Stephen W. Melvin and {Wen-mei} Hwu
and Michael C. Shebanow",
title = "Critical Issues Regarding {HPS}, a High Performance Microarchitecture",
crossref = "micro85",
pages = "109--116",
annote = "Discusses in depth some of the issues in dynamic
scheduling hardware."
}
@Proceedings{micro85,
key = "MICRO-18",
booktitle = "The $18^{th}$ Annual Workshop on Microprogramming
(MICRO-18)",
title = "The $18^{th}$ Annual Workshop on Microprogramming
(MICRO-18)",
year = "1985",
}
@InProceedings{hwu&patt87isca,
author = "{Wen-mei} Hwu and Yale N. Patt",
title = "Checkpoint Repair for Out-of-order Execution Machines",
crossref = "isca87",
pages = "18--26",
note = "Newer version: \cite{hwu&patt87ieeetc}",
annote = "Describes design issues in checkpoint mechanisms for
precise interrupts and speculative execution. Their
design uses backup register files and difference
techniques for main memory. Instructions can be
retired out-of-order, avoiding full window
conditions."
}
@Article{hwu&patt87ieeetc,
author = "{Wen-mei} Hwu and Yale N. Patt",
title = "Checkpoint Repair for High-Performance Out-of-order
Execution Machines",
journal = ieeetc,
year = "1987",
volume = "36",
number = "12",
pages = "1496--1514",
month = dec
}
And there's also some other relevant work from the time:
@Article{smith&pleszkun88,
author = "James E. Smith and Andrew R. Pleszkun",
title = "Implementing Precise Interrupts in Pipelined Processors",
journal = ieeetc,
year = "1988",
volume = "37",
number = "5",
pages = "562--573",
month = may,
annote = "After defining precise interrupts this papaer
describes several ways to achieve them in pipelined
machines: Plain in-order completion is slow, because
new instructions must wait longer for the results. To
resolve the problem, the paper presents in-order
completion with bypasses, history buffers and future
files (a shadow register file that keeps the
imprecise state). Stores should be issued immediately
and buffered in the memory unit to avoid performance
problems. A performance analysis is done (on a
high-latency model) and extensions to virtual memory,
cache memory, and vectors are discussed."
}
- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html |
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