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Fawnizu
Guest
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 Posted:
Thu Aug 11, 2005 8:15 am Post subject:
SoC bus architecture (typical) |
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Hello,
Hope someone who has been involved in SoC design can help me with some
information regarding the typical SoC bus architecture used.
1. Does it use just generic bus (only data lines)?
2. Or does it use standard bus, i.e. PCI, AMBA, etc?
3. What is the typical bus standard used by SoC designers?
Appreciate any input.
Thank you,
Fawnizu |
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Guest
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| Posted:
Thu Aug 11, 2005 4:15 pm Post subject:
Re: SoC bus architecture (typical) |
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I can tell you that the pathways through the NorthBridge portion of
Opterons look a lot more like CPU data-manipulation pipelines than any
chip to chip bus ever conceived. |
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Del Cecchi
Guest
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| Posted:
Thu Aug 11, 2005 10:41 pm Post subject:
Re: SoC bus architecture (typical) |
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Fawnizu wrote:
| Quote: | Hello,
Hope someone who has been involved in SoC design can help me with some
information regarding the typical SoC bus architecture used.
1. Does it use just generic bus (only data lines)?
2. Or does it use standard bus, i.e. PCI, AMBA, etc?
3. What is the typical bus standard used by SoC designers?
Appreciate any input.
Thank you,
Fawnizu
|
IBM has a bus called "core connect" that a number of its cores use.
Documentation is available on the web. If you are doing a SOC by using
IP from someone you have to connect to the IP in a way that the designer
wants you to. If you are doing your own IP then you can do what you
want. Using a standard external bus would be silly.
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.” |
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Peter \"Firefly\" Lund
Guest
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| Posted:
Thu Aug 11, 2005 10:52 pm Post subject:
Re: SoC bus architecture (typical) |
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On Thu, 11 Aug 2005, Del Cecchi wrote:
| Quote: | IBM has a bus called "core connect" that a number of its cores use.
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I think there are some SoC's that use AMBA.
There's also wishbone.
-Peter |
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Fawnizu
Guest
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| Posted:
Sat Aug 13, 2005 2:13 pm Post subject:
Re: SoC bus architecture (typical) |
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Del Cecchi,
Thanks for your input. Thanks also to Mitch and Peter.
I would like to clarify on the "If you are doing a SOC by using
IP from someone you have to connect to the IP in a way that the
designer
wants you to" statement. So, if I use many different IPs from different
designers, I have to follow their required design requirements? If each
of them use different protocols (say, A uses PCI, B uses AMBA, C uses
"core connect", etc), what is my option to make all of them
communicate? I hope it does not require me to implement all those bus
standards in my SoC.
Fawnizu |
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Ronald H. Nicholson Jr.
Guest
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| Posted:
Sat Aug 13, 2005 7:34 pm Post subject:
Re: SoC bus architecture (typical) |
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In article <1123741893.853406.72480@g43g2000cwa.googlegroups.com>,
Fawnizu <fawnizu@gmail.com> wrote:
| Quote: | Hope someone who has been involved in SoC design can help me with some
information regarding the typical SoC bus architecture used.
1. Does it use just generic bus (only data lines)?
2. Or does it use standard bus, i.e. PCI, AMBA, etc?
3. What is the typical bus standard used by SoC designers?
|
Depends on what you mean by "bus". This could refer to just about any
bundle of signals, but sometimes refers to some consistent protocol which
the various IP blocks on a SoC use to communicate with a processor or
memory subsystem.
There are several different bus protocols in use by SoC designers,
including CoreFrame (Palmchip), AMBA (ARM), CoreConnect (IBM), Wishbone
(Opencores), etc. Some older SoC designs even try to emulate a PC bus
protocols, such as PCI, internally; but the use of true bidirectional
wires inside a submicron ASIC presents various some interesting design
and test issues. Many companies homebrew their own internal interconnect
protocol, including things that look more like a pipelined router matrix
than a PC system bus. None seems more "typical" than another IMO.
An SoC designer will typically use either use IP blocks which implement
only one selected bus standard, or develop or buy bus interfaces and
bus protocol converters for alien IP blocks as needed.
IMHO. YMMV.
--
Ron Nicholson rhn AT nicholson DOT com http://www.nicholson.com/rhn/
#include <canonical.disclaimer> // only my own opinions, etc. |
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Del Cecchi
Guest
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| Posted:
Sun Aug 14, 2005 4:15 pm Post subject:
Re: SoC bus architecture (typical) |
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"Fawnizu" <fawnizu@gmail.com> wrote in message
news:1123924396.587337.172650@g47g2000cwa.googlegroups.com...
| Quote: | Del Cecchi,
Thanks for your input. Thanks also to Mitch and Peter.
I would like to clarify on the "If you are doing a SOC by using
IP from someone you have to connect to the IP in a way that the
designer
wants you to" statement. So, if I use many different IPs from different
designers, I have to follow their required design requirements? If each
of them use different protocols (say, A uses PCI, B uses AMBA, C uses
"core connect", etc), what is my option to make all of them
communicate? I hope it does not require me to implement all those bus
standards in my SoC.
|
If you were building a board with a bunch of components on it and the
processor had hyper transport, and the memory is DDR2 and the other
memory is RDram and the Video is PCI express and the disk is eide etc.
you would have to implement all those standards. An SOC is same deal.
So you need to pick your IP with an eye on the interfaces required. That
may mean getting most of the IP from a single source. If you are using
IBM ASICs that is probably coreconnect and IBM IP. If you are using TSMC
Foundry, then some other bus and IP supplier would perhaps be better.
del
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Fawnizu
Guest
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| Posted:
Mon Aug 15, 2005 8:15 am Post subject:
Re: SoC bus architecture (typical) |
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Ron and everyone,
So can I safely say that SoC designers DON'T use "a bundle of signals"
as the bus to interface all the cores? Instead, some sort of
standardized bus is used. Which bus standard would probably depend on
who (and from where) I'm talking to...as you've mentioned.
Are these bus standards (documents that describe the standard AND RTL
implementation of them) publicly available? Where can I obtain them?
For example, AMBA, CoreConnect, CoreFrame.
I can probably find Wishbone implementation and documentation from the
opencores.org website. I'll check this one.
Thank you all for your input.
Fawnizu |
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Del Cecchi
Guest
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| Posted:
Mon Aug 15, 2005 4:15 pm Post subject:
Re: SoC bus architecture (typical) |
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Fawnizu wrote:
| Quote: | Ron and everyone,
So can I safely say that SoC designers DON'T use "a bundle of signals"
as the bus to interface all the cores? Instead, some sort of
standardized bus is used. Which bus standard would probably depend on
who (and from where) I'm talking to...as you've mentioned.
Are these bus standards (documents that describe the standard AND RTL
implementation of them) publicly available? Where can I obtain them?
For example, AMBA, CoreConnect, CoreFrame.
I can probably find Wishbone implementation and documentation from the
opencores.org website. I'll check this one.
Thank you all for your input.
Fawnizu
|
Here is a page that will start you out with Core Connect
http://www-306.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture
If one is making a variety of cores that need to talk to each other it
would be stupid for them each to have some goofy ad hoc interface.
Rather they should all have a standard interface for the whole bunch of
them. That would seem obvious.
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.” |
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