Joe Seigh
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 Posted:
Fri Aug 19, 2005 4:15 pm Post subject:
RCU+SMR hazard pointers w/o memory barriers |
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I have a subproject on my site
http://atomic-ptr-plus.sourceforge.net/
That uses a modified RCU to remove the need for
memory barriers in SMR hazard pointers. The memory
barriers can really slow things down on a pipelined
processor, or conversly you can say that pipelining
can really speed things up without them. Timing of
hazard pointer loads w/o memory barriers and with memory
barriers (store/load plus a second release memory barrier) is
11 nsec and 78 nsec repectively on a 866 mhz P3 and
10 nsec and 115 nsec respectively on a 1.2 ghz ppc.
This makes a big difference in traversing a linked list
for example. The proxy usage pattern is even faster
since there is only one hazard pointer load and normal
dependent loads for list traversal.
This will help as we go to multi-core cpus as it
scales better than conventional syncrhonization and is
more cache friendly.
This might be one of the few times where software design
overtook hardware instead of hardware dictating the
programming model.
--
Joe Seigh
When you get lemons, you make lemonade.
When you get hardware, you make software. |
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