| Author |
Message |
Stefan Duenser
Guest
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 Posted:
Thu Jan 06, 2005 9:15 pm Post subject:
is this memory implementation synthesizeable? |
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Hi all
I have implemented a very easy memory with a few registers, where i can
store and also read values for and from my ALU:
I have got 2 questions:
1) The conv_integer procedure does not work here, I always get the
errormessage: no feasable subprogram entry for conv_integer. Any ideas whats
wrong here?
2) Finally this memory should be synthizeable for a Xilinx ML300 board. What
do I have to change that this will be alright?
Is there a documention available? I wasnt able to find one online, which
says me in a detailed way what constructs I can use!
Thanks for any useful hints
SD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity memory is
generic (width : integer := 32);
port (clk : in std_ulogic;
rst : in std_ulogic;
inp : in std_ulogic_vector((2*width-1) downto 0);
addr: in std_ulogic_vector(3 downto 0);
wr : in std_ulogic;
rd : in std_ulogic;
outp: out std_ulogic_vector((2*width-1) downto 0)
);
end memory;
architecture rtl of memory is
type reg_type is array (0 to 3) of std_ulogic_vector((2*width-1) downto
0);
signal reg_file : reg_type;
begin
write : process(clk,rst,inp,addr,wr)
variable x_int : integer;
begin
if rst = '1' then
reg_file(0) <= (others => '0');
else
if clk'event and clk = '1' then
if wr = '1' then
reg_file(conv_integer(addr)) <= inp;
end if;
end if;
end if;
end process;
read : process(clk,rst,addr,rd)
begin
if rst = '1' then
outp <= (others => '0');
else
if clk'event and clk = '1' then
if rd = '1' then
outp <= reg_file(conv_integer(addr));
end if;
end if;
end if;
end process;
end rtl; |
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Tim
Guest
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| Posted:
Thu Jan 06, 2005 11:14 pm Post subject:
Re: is this memory implementation synthesizeable? |
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"Stefan Duenser" wrote
| Quote: | Hi all
I have implemented a very easy memory with a few registers, where i can
store and also read values for and from my ALU:
I have got 2 questions:
1) The conv_integer procedure does not work here, I always get the
errormessage: no feasable subprogram entry for conv_integer. Any ideas whats
wrong here?
|
On this one, comp.lang.vhdl is the place for the VHDL questions.
If you check the archive you will see a zillion repetitions of
this advice: use the numeric_std library
Then you can use to_integer().
I usually use an indirect function to clean up the simulation:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
function ToInteger(ARG: UNSIGNED) return INTEGER is
variable x: unsigned(ARG'range);
variable n: integer;
begin
x := ARG;
-- synthesis translate_off
for i in x'range loop
if x(i)/='1' then -- resolve the 'undefined' signals
x(i) := '0';
end if;
end loop;
-- synthesis translate_on
n := to_integer(x);
return n;
end; |
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Stefan Duenser
Guest
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| Posted:
Thu Jan 06, 2005 11:16 pm Post subject:
Re: is this memory implementation synthesizeable? |
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| Quote: | 1) The conv_integer procedure does not work here, I always get the
errormessage: no feasable subprogram entry for conv_integer. Any ideas
whats wrong here?
|
I really dont understand why this is not working, because this functions are
declared in the ieee.std_logic_arith.all header...
FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN
INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN
INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
NATURAL;
FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 )
RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 )
RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN
NATURAL;
FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN
NATURAL;
FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER
any useful tips? |
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Jonathan Bromley
Guest
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| Posted:
Thu Jan 06, 2005 11:33 pm Post subject:
Re: is this memory implementation synthesizeable? |
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On Thu, 6 Jan 2005 18:16:41 -0000,
"Stefan Duenser" <carlsberg@gmx.at> wrote:
| Quote: | 1) The conv_integer procedure does not work here, I always get the
errormessage: no feasable subprogram entry for conv_integer. Any ideas
whats wrong here?
I really dont understand why this is not working, because this functions are
declared in the ieee.std_logic_arith.all header...
|
[snip]
Take heed of what the nice man said: USE NUMERIC_STD.
Like many other people, you have unnecessarily included
both
use ieee.std_logic_arith.all;
and
use ieee.std_logic_unsigned.all;
I think one of the Xilinx tools tends to add both
these clauses by default - silly thing to do.
Your problem is caused because CONV_INTEGER() is
defined in BOTH packages. Consequently, neither
definition is visible. You could, if you were
desperate, use a fully-qualified function name:
int <= ieee.std_logic_arith.conv_integer(vec);
but that would be silly, wouldn't it?
So PLEASE, get rid of std_logic_arith and
std_logic_[un]signed from all your code, start
using numeric_std instead, and read comp.lang.vhdl
for lots of advice on how to do that.
The quick fix is for you to remove one of the two
use clauses, but it's way better to do it properly.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated. |
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