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arun · Guest

Hi

I have been trying to find out on the internet as to how FSB frequency
is assigned to a particular processor, but I have not yet found out.
I understand that common FSB numbers are 133, 400, 533, 800MHz and also
about the processor core frequency being some multiple of this number.
What I fail to understand is, how is the bus frequency determined?

I think, processor clock cycle time (core frequency) is based on the
commonly used longest combinational circuit path time OR something in
that lines.
Does that influence the FSB speed? How is the FSB speed determined and
why is it so less compared to Processor speed?

I'd greatly appreciate if somebody helps me out.

Thanks.
-Arun.

Bill Bradley · Guest

arun wrote:

Guest

A long time ago (about the 80386 time period) some company started to
use 33 MHz for the FSB. And the processors operated at 1:1 with respect
to the FSB frequency. Later the FSB frequency was increased to 66 MHz
in various steps and the electricals of the FSB were simply beaten into
submission. After 66 MHz the FSB electricals could not longer be beaten
into submission.

At the other end of the FSB were the North Bridge and South Bridge
parts that when running at 66 MHz had "plenty of bandwidth (for the
time period). With the NB and SB happily operating at 66 MHz, and the
eminent arrival of the next generation processors that could operate at
100-133 MHz, a simple 2X frequency multiplier could couple the fast
processor to the slower FSB. Making the bus 2X as wide aleviated the BW
issues.

With frequency multiplication based on the speed of the NB and SB
parts, a generous range of frequencies could be delivered into the
market in timely fassion. Using 50 MHz and 66 MHz, you get the
progression 50 MHz, 66 MHz, 100 MHz, 133 Mhz, 150 MHz, 200 MHz, 250
MHz, 266 MHz,.....all the way into the 3-4 GHz range. Somewhere in the
400 MHz CPU range the 50MHz sub-multiple was dropped and 66 MHz became
the only 'interesting' FSB base frequency.

Intel systems are based on the 66 MHz number as a legacy back to this
ear. AMD parts are based on a 100 MHz base frequency legacy AMD
inhereted from DEC for the first FSB on Athlon.

At this juncture in time, this base frequency is not used for other
than a base frequency (outside of the South Bridge) and all operations
are based on mulples from this base. This includes the frequency and
data rates of the 'busses', CPU and caches.

Since the days of 100 MHz processors, the FSB frequency has primarily
been driven by the pin electronics and the control of the external
impeadance on the motherboard. You might note that while the data rates
on these busses ahs risen dramatically (66 MHz has become 1+ GHz) the
latency from inside one chip to inside another chip properly
latched/registered has only gone down from ~13ns to ~9ns. Basicaly the
FSBs have been pipelined to death to achieve these data rates while the
physics of interconnect has remained stubornely fixed.

arun · Guest

Thanks to Bill and Mitch for your replies.

According to Bill, DRAMs are slower, so increasing FSB speeds wouldn't
help.
And according to Mitch, improvement in FSB datarate has been due to
pipelining of the bus and not because of bus frequency increase.

So Mitch, are you saying that busses on motherboards are the same
(physically etc) in case of both a 400MHz FSB and 533 MHz FSB
processors; just that the processor and the chipset make use of the bus
more efficiently in the latter case!
And is that is the reason why FSB speed is a characteristic of a
processor?

Because I have wondered before why FSB speed is a parameter of the
processor when it should actually be a parameter of motherboard. Now I
am thinking that, bus is the same resource in every motherboard,
different processors and chipsets make use of the resource at
differently (datarates).

Mitch, could you please comment on my inference.

-Arun.

Del Cecchi · Guest

arun wrote:

Guest

What I was trying to indicate is that the frequency (rate at which data
passes ove a bus) has gone up as technology advances, but the latency
to get from inside one chip (say a CPU) to the (say) NorthBridge chip
has remaind rather constant. In the very old days (circa 1980) a signal
was driven out a pin from a register inside the chip, across the wire,
and latched into the destination chip before the driver on the sending
chip quit asserting this signal. Now, however, the data rate is such
that the driver sending the signal switches to sending its successor
(and sometimes its successors' successor) before the first signal is
latched in the receiving chip. That is; several signals are present on
a single piece of wire simultaneously. This takes great control over
the electrical characteristics of the driver, receiver, the clocking of
the signals, and control over the wire impeadances that the signal
traverses. In 1980 we did not have tools, or materials to control
impedances to the required degree within reasonable cost structures
(ECL could; LV-TTL could not).

Does a FSB operating at 400 MHz physically 'look' like the FSB of a 533
MHz? Yes, and indeed many 533MHZ FSBs are down clocked to 400 MHz just
because its simply and easy to do. However, if you have an FSB that
runs at 400 MHz it can be nearly impossible to upclock it to operate at
533 MHz UNLESS you have done all the electrical engineering work for it
to be a 533 MHz part. E.G. Downbinning is easy, upbinning can be
impossible.

FSB is a divide down of the processor frequency because this avoid
having to use synchronizers to cross clock domains from the high
frequencies of the processors (say 3 GHz) to the low frequency of the
FSB (3,000 MHz / 6 = 500 MHz FSB or 3,000 MHz / 7 = 428.57 MHz). As
long as the FSB frequency can be divided down to a number not greater
than the electrical environment on the motherboard, the system should
'run'. So, the motherboard sets the upper limit of the FSB, and the
processor is configured to choose the largest FSB frequency that does
not exceede the motherboard capabilities.

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