Intel x86 memory model question

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Joe Seigh
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Posted: Sat Oct 22, 2005 9:25 pm Post subject: Re: Intel x86 memory model question

Alexander Terekhov wrote:

Quote:

Joe Seigh wrote: ...

http://www.decadentplace.org.uk/pipermail/cpp-threads/2005-October/000728.html

quote

Enough people from Intel who can speak authoritatively about this
for me to confidently believe it have said (a) "locked" instructions
and mfence DO have global ordering properties on current and
near-future x86s (b) Intel now realizes that this should have been
documented and will try to ensure that it is (c) Intel does not want
to promise that this will hold forever, and might be interested in
engaging with different language-level standards groups to see if
there is a way to weaken total SC-ness of lock/volatile/atomic specs
to avoid multiple observer ordering agreement requirements that do not
impact practical programs.

/quote

I'm not in cpp-threads anymore, the moderation time lag was insane, so I can't

reply there. However I would think the standards groups would want to avoid
a meta memory model in their definitions to give the hardware as much
flexibility as possible in its memory model definitions.

--
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

David Hopwood
Guest

Posted: Sun Oct 23, 2005 6:16 am Post subject: Re: Intel x86 memory model question

Alexander Terekhov wrote:

Quote:

This is rather vague. I assume it must mean at least that locked instructions
and mfence perform in a total order that is the same for all processors. But
no program is going to use *just* locked accesses and mfences. So how does
this interact with other accesses?

Quote:

(b) Intel now realizes that this should have been
documented and will try to ensure that it is (c) Intel does not want
to promise that this will hold forever, and might be interested in
engaging with different language-level standards groups to see if
there is a way to weaken total SC-ness of lock/volatile/atomic specs
to avoid multiple observer ordering agreement requirements that do not
impact practical programs.

/quote

Are these instructions typically executed frequently enough for any relaxation
of their ordering semantics to be worthwhile?

Intel (and AMD) should IMHO wait until the software and standards situation has
settled down a bit before attempting to weaken their hardware. The x86 variant
of processor consistency, with total ordering for some instructions, is fine
for the time being. It just needs to be better documented (e.g. something like
<http://www.intel.com/design/itanium/downloads/25142901.pdf> for x86[-64]).

--
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

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