Multicore bus architecture
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Multicore bus architecture

 
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Fawnizu
Guest
Posted: Thu Sep 08, 2005 8:15 am    Post subject: Multicore bus architecture Reply with quote
Hi,

It's interesting to see that now the processor giants (Intel, AMD, etc)
are now switching their interests on core counts rather than MHz like
it used to be. So I guess now the more important design improvement is
intercore communication.

Does anybody know what kind of bus architecture is currently being
pursued (or suitable) for multicore chips? I suppose it won't be the
same as the single core bus architecture.

Care to shed some light?

Fawnizu
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cybersnn
Guest
Posted: Thu Sep 08, 2005 8:15 am    Post subject: Re: Multicore bus architecture Reply with quote
each core of dualcore of h.t processors has the register
files,internal schedulers, scalar units .it follows inorder issue and
inorder retirement .afore mentioned facts reflect to wat degree is the
core processing extended.it is symmetric multi processing. there is
very less to bother about inter core communication ,the connecting
control signals are used only for resource locking and privileges like
bus master and some other.interface to f.s.b is multi plexed withsome
intermediate logic
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