SGI finally on its last legs?
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SGI finally on its last legs?
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Bill Davidsen
Guest





Posted: Tue Sep 13, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

vince@offshore.ai wrote:
Quote:
You want to bet that nine women can have a baby in one month?


Supercomputers today use lots of processors and applications are
designed for this.

The term applications is ambiguous here. If you mean the problems, they
are not designed, they exist, and may or may not be amenable to parallel
solutions (more pedanticaly solutions using parallel computation). If
you mean the application code, which I assume you do, sometime you can
do parallel computations and sometimes the problem is linear.

The big benefit of the Cray2 was that it was fast for linear vector
computations, and could solve problems which were inherently linear.

--
bill davidsen
SBC/Prodigy Yorktown Heights NY data center
http://newsgroups.news.prodigy.com
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Del Cecchi
Guest





Posted: Tue Sep 13, 2005 4:15 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

Alex Johnson wrote:
Quote:
Del Cecchi wrote:

My guess is that he had decided to transition to Intel for business
reasons, and the notion that Itanium would be a technical flop never
occurred to him. Besides, what choice did he have?


Choose your words more carefully. Itanium was not a technical flop.
Well, the original was, but SGI did not abandon MIPS until Itanium II
was declared the world's most powerful microprocessor for numerically
intensive applications (ie, scientific computing, SGI's primary client
base) after knocking the previous title holder, Power 4, from that spot
in mid-02.

Alex

You are right, I should have said "MIGHT BE a technical flop", (in that
it wouldn't meet the needs of a wide customer set) or "MIGHT BE a
(plain) flop", meaning mostly in a business sense. I guess the jury is
still out on the issue of Itanium's long term future. At least in my
view, not that I have any special knowledge.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
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Alex Johnson
Guest





Posted: Tue Sep 13, 2005 4:15 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

Del Cecchi wrote:
Quote:
My guess is that he had decided to transition to Intel for business
reasons, and the notion that Itanium would be a technical flop never
occurred to him. Besides, what choice did he have?

Choose your words more carefully. Itanium was not a technical flop.
Well, the original was, but SGI did not abandon MIPS until Itanium II
was declared the world's most powerful microprocessor for numerically
intensive applications (ie, scientific computing, SGI's primary client
base) after knocking the previous title holder, Power 4, from that spot
in mid-02.

Alex
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Rupert Pigott
Guest





Posted: Tue Sep 13, 2005 4:15 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

John Savard wrote:

[SNIP]

Quote:
You want to bet that nine women can have a baby in one month?

At present, in Opteron land, according to www.spec.org, you would
need ~1.3 women to have a floating point baby in 9 months. OTOH
you would need just ~0.9 women to have an integer baby in 9 months.

That doesn't seem like a big gap to me, a proportion of that gap
could well be down to cache size disparity (1Mbyte vs 9Mbyte).
That is not a massively hard thing for AMD to fix, but it is an
expensive fix to fabricate.

Quote:
Yes, Itanium will soon be history if it remains as badly overpriced as
it is. If Intel is capable of making a multicore Itanium with any yield

It has to be expensive, 3 to 9Mbytes of cache is a huge chunk of
silicon. It would be interesting to see what a K8 core could do
with 8Mbyte of L2 cache.

Cheers,
Rupert
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Guest






Posted: Tue Sep 13, 2005 9:17 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren wrote:
Quote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.



dk

No, memory arrays in shared cache don't have to be multiported.

AFAIK, Power4/5 shared L2 cache is built of single-ported arrays.
Multiported SRAM is too expensive in terms of gates/bit. Instead, you
build your cache of multiple banks (you will build it in such manner
anyway for many other reasons) and allow simultaneous access to
different banks. And when there is a bank conflict - one agent forced
to wait. It's really not principally different from the situation with
non-shared L2 cache that has to serve concurrent L1C and L1D accesses.
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Guest






Posted: Tue Sep 13, 2005 9:37 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

vince@offshore.ai writes:

Quote:
John Savard wrote:

If you're making supercomputers, and you can't make your own chips like
Cray or NEC, the Itanium _is_ the best choice, since it offers the most
performance *per core*.

I think the following 4 ratios are each more important than per core
performance:

1) price/performance
2) performance/socket

Not so by a long shot. Someone recently replaced 833MHz EV6s with 6
month ago fastest mostest AMDs. FP throughput is about 1/2 what it was
at best. Note that any EV6 is not the real bleeding edge anymore.

Quote:
3) performance/watt
4) performacne/rack

--
Paul Repacholi 1 Crescent Rd.,
+61 (08) 9257-1001 Kalamunda.
West Australia 6076
comp.os.vms,- The Older, Grumpier Slashdot
Raw, Cooked or Well-done, it's all half baked.
EPIC, The Architecture of the future, always has been, always will be.
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Guest






Posted: Tue Sep 13, 2005 10:38 pm    Post subject: Re: SGI finally on its last legs? Reply with quote

Quote:
That doesn't seem like a big gap to me,

Opterons just got about 10% faster in the last couple days. Sun/AMD
announced some 120 watt Opterons that are like 10% faster. So the
floating point gap is noise at this point. Opteron's integer lead is
bigger though.

The other thing is that when you put 4 Opterons together you get very
nearly 4 times the performance with no glue chips. This is not so with
Itanium. So the Opteron price/performance lead is even better once we
are talking about real systems and not just 1 CPU.
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Guest






Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren wrote:
Quote:
already5chosen@yahoo.com> wrote in message
news:1126628242.886463.291650@g43g2000cwa.googlegroups.com...

Dan Koren wrote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.

No, memory arrays in shared cache
don't have to be multiported.



They don't have to, but it would
certainly help performance.


dk

Don't be so sure.
You need to arbitrate between writes from one agent and reads/writes to
the same location from all other agents regardless of number of ports.
Since value propagation through dual-ported memory takes several
cycles, arbitration machine wouldn't be particularly simple.
Also, since multiported memory cells are bigger (+2T for each
additional port), the whole array becomes less dense. It means - longer
wires. As you probably heard, nowadays long wires considered harmful.
So at the end of the day you have both bigger die and the same or
slower speed.
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Guest






Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren wrote:
Quote:
already5chosen@yahoo.com> wrote in message
news:1126628242.886463.291650@g43g2000cwa.googlegroups.com...

Dan Koren wrote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.

No, memory arrays in shared cache
don't have to be multiported.



They don't have to, but it would certainly help performance.


Don't be so sure.
You need to arbitrate between writes from one agent and reads/writes to
the same location from all other agents regardless of number of ports.
Since value propagation through dual-ported memory takes several
cycles, arbitration machine wouldn't be particularly simple.
Also, since multiported memory cells are bigger (+2T for each
additional port), the whole array becomes less dense. It means - longer
wires. As you probably heard, nowadays long wires considered harmful.
So at the end you have both bigger die and the same or slower speed.
Back to top
Guest






Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren wrote:
Quote:
already5chosen@yahoo.com> wrote in message
news:1126628242.886463.291650@g43g2000cwa.googlegroups.com...

Dan Koren wrote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.

No, memory arrays in shared cache
don't have to be multiported.


They don't have to, but it would certainly help performance.


Don't be so sure.
You need to arbitrate between writes from one agent and reads/writes to
the same location from all other agents regardless of number of ports.
Since value propagation through dual-ported memory takes several
cycles, arbitration machine wouldn't be particularly simple.
Also, since multiported memory cells are bigger (+2T for each
additional port), the whole array becomes less dense. It means - longer
wires. As you probably heard, nowadays long wires considered harmful.
So at the end you have both bigger die and the same or slower speed.
Back to top
Guest






Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren wrote:
Quote:
already5chosen@yahoo.com> wrote in message
news:1126628242.886463.291650@g43g2000cwa.googlegroups.com...

Dan Koren wrote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.

No, memory arrays in shared cache
don't have to be multiported.



They don't have to, but it would
certainly help performance.


dk

Don't be so sure.
You need to arbitrate between writes from one agent and reads/writes to
the same location from all other agents regardless of number of ports.
Since value propagation through dual-ported memory takes several
cycles, arbitration machine wouldn't be particularly simple.
Also, since multiported memory cells are bigger (+2T for each
additional port), the whole array becomes less dense. It means - longer
wires. As you probably heard, nowadays long wires considered harmful.
So at the end of the day you have both bigger die and the same or
slower speed.
Back to top
Dan Koren
Guest





Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

<prep@prep.synonet.com> wrote in message
news:87br2wapqj.fsf@prep.synonet.com...
Quote:
vince@offshore.ai writes:

John Savard wrote:

If you're making supercomputers, and you can't make your own chips like
Cray or NEC, the Itanium _is_ the best choice, since it offers the most
performance *per core*.

I think the following 4 ratios are each more important than per core
performance:

1) price/performance
2) performance/socket

Not so by a long shot. Someone recently replaced 833MHz EV6s with 6
month ago fastest mostest AMDs. FP throughput is about 1/2 what it was
at best. Note that any EV6 is not the real bleeding edge anymore.


Certainly not.

It still is the frying edge though! ;-)


dk
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Dan Koren
Guest





Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

<already5chosen@yahoo.com> wrote in message
news:1126628242.886463.291650@g43g2000cwa.googlegroups.com...
Quote:

Dan Koren wrote:
"Dan Koren" <dankoren@yahoo.com> wrote in message
news:43249e75$1@news.meer.net...

\"Greg Lindahl" <lindahl@pbm.com> wrote in message
news:4324934a$1@news.meer.net...
In article <43241db8.4481061@news.usenetzone.com>,
John Savard <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

Multicore, as opposed to multi-chip,
offers only one technical benefit -
faster access to a shared cache.

Er, no, a shared cache is actually
more cycles in the uncontended case.
^^^^^^^^^^^
---------------------+++++++++++


Why? Do you think there is some
inherent reason, or it is just
an artifact of current designs?



Obviously to support two cores or
processors efficiently, a cache
would have to be dual- or multi-
ported. Beyond which I cannot
see any obstacles.

No, memory arrays in shared cache
don't have to be multiported.



They don't have to, but it would
certainly help performance.


dk
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Rupert Pigott
Guest





Posted: Wed Sep 14, 2005 12:15 am    Post subject: Re: SGI finally on its last legs? Reply with quote

prep@prep.synonet.com wrote:

[SNIP]

Quote:
Not so by a long shot. Someone recently replaced 833MHz EV6s with 6
month ago fastest mostest AMDs. FP throughput is about 1/2 what it was
at best. Note that any EV6 is not the real bleeding edge anymore.

Is that simply a matter of tuning, poor compilers or what ? Sounds
like a pathological case being tickled.

Cheers,
Rupert
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Sander Vesik
Guest





Posted: Wed Sep 14, 2005 3:30 am    Post subject: Re: SGI finally on its last legs? Reply with quote

Dan Koren <dankoren@yahoo.com> wrote:
Quote:

They don't have to, but it would
certainly help performance.


Only if data accesses (tag access is completely different issue)
by more than one core are frequent enough that it pays off for
the loss in speed (never mind loss in cost) for having more than
one port. If you have a multi-way - or even just multibank - cache
the benefit of having more than one port on the data rows
vanishes a lot faster.

If you were sharing a L1 cache you would probably want multiple
ports for the cores, but L1 sharing is OTOH probaly also not
what you want to do.

Quote:

dk



--
Sander

+++ Out of cheese error +++
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