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Yxan
Guest
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 Posted:
Wed Dec 08, 2004 4:51 pm Post subject:
jtag, boundary scan, TAP ....??? |
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jtag, boundary scan, TAP, ICE ...
I'm new to 'jtag' and the stuff/modules included in it.
What is boundary scan? (Just used to identify chips??)
What is ICE? (Just used for debuging, read/write to registers???)
I need some webpage that will learn me the basics.
Is there any freeware that will identify any chips located on a "jtag chain".
/Yxan/ |
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Tauno Voipio
Guest
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| Posted:
Thu Dec 09, 2004 12:16 am Post subject:
Re: jtag, boundary scan, TAP ....??? |
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Yxan wrote:
| Quote: | jtag, boundary scan, TAP, ICE ...
I'm new to 'jtag' and the stuff/modules included in it.
What is boundary scan? (Just used to identify chips??)
What is ICE? (Just used for debuging, read/write to registers???)
I need some webpage that will learn me the basics.
Is there any freeware that will identify any chips located on a "jtag chain".
|
JTAG is a chip test standard originally by the
Joint Test Action Group. Currently the corresponding
standard is IEEE 1149.
TAP is Test Access Port in the standard. It is a state-machine
device on a JTAG-enabled chip. The state machine enables the
tester to control the test electronics with one clock, one control,
one data in and one data out signal.
The TAP and associated data ports are designed so that
several chips using the ports may be chained together,
so that the chips are seen as a single test port to the
test equipment.
Boundary scan is a test method where specially constructed
shift register cells are placed between the chip innards and
the corresponding I/O pins. The calls enable (under TAP control)
to read and set the pin signals and the signals from the
pins to and from the chip internals.
ICE is usually In-Circuit Emulator, a piece of hardware
added to a processor chip to help debugging the hardware
and software with the processor. Pretty often the registers
in the ICE are controlled via the JTAG port (under TAP control).
HTH
--
Tauno Voipio
tauno voipio (at) iki fi |
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Cliff Brake
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