arun
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 Posted:
Fri Nov 18, 2005 3:31 pm Post subject:
Simplescalar cache_access( ) question |
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Hello:
This is a Simplescalar simulator code question.
In SS 3.0, cache is accessed using a cache_access( ) function. In case
of write hit, shouldn't the 'ready' variable of the cache block
structure be changed to (now+hit_latency), when there are no
outstanding misses? If we return hit_latency when there is a read hit,
why does the same not apply on a write hit?
Currently, ready is changed only in the cache miss section to a future
cycle time equal to miss latency of that cache access.
Thanks in advance to anyone commenting on this question.
-Arun. |
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