Altera equivalent for Xilinx's "async_reg" attribute
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Altera equivalent for Xilinx's "async_reg" attribute

 
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Nicolas Matringe
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Posted: Wed Dec 01, 2004 7:54 pm    Post subject: Altera equivalent for Xilinx's "async_reg" attribute Reply with quote
Hello
The question is in the subject: is there such a thing?
How to make an Altera post-p&r simulation work when a setup violation
occurs on an input register?
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
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MikeTreseler
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Posted: Wed Dec 01, 2004 11:39 pm    Post subject: Re: Altera equivalent for Xilinx's Reply with quote
http://groups.google.com/groups?q=flops+trust+synchronizer+setup/hold

-- Mike Treseler
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rickman
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Posted: Thu Dec 02, 2004 12:43 am    Post subject: Re: Altera equivalent for Xilinx's "async_reg" attribute Reply with quote
Nicolas Matringe wrote:
Quote:

Hello
The question is in the subject: is there such a thing?
How to make an Altera post-p&r simulation work when a setup violation
occurs on an input register?

How about synching the testbench data output to the chip input clock? I
don't think there is any value to allowing the setup time to be violated
in a simulation since there is no simulation equivalent to
metastability.

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Rick "rickman" Collins

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