glen herrmannsfeldt
Guest
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 Posted:
Sat Dec 11, 2004 12:36 am Post subject:
Re: 30bit - adder performance improvement |
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ALuPin wrote:
| Quote: | Using a Cypress VHDL template for a 30bit adder I face the problem
that I have to activate an internal pipeline stage within the template
to get the performance I need.
Using this pipeline stage the output of the adder is only valid
every two clock cycles.
Is it possible to split the addition into two adders and to
combine the results that way so that I get a valid sum every
clock cycle ?
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You mean the carry delay is too long?
Split it into two adders, maybe 16 and 14 or 15 and 15, and pipeline
the carry between them. The two will then be one pipeline stage
apart, which may complicate the rest of the pipeline.
Not knowing what the rest of your logic looks like, you might
look into carry save adders. When adding more than two numbers,
a carry save adder pipeline saves the carry propagation until the
last step.
Though I would expect a pipelined template adder to be fully
pipelined, such that you would get a new result out every cycle,
though delayed the appropriate number of cycles. At each clock
cycle you put in A(t) and B(t) and get out sum(t-2) or sum(t-3).
-- glen |
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