| Author |
Message |
Yingxia Wang
Guest
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 Posted:
Fri Feb 04, 2005 6:16 am Post subject:
A new computer architecture |
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Dear All:
Please visit my site at:
http://mysite.verizon.net/~vze26krk/CPM.html
There, I will discuss the end of Moore's law, and a new computer
architecture with I have proposed in 2003. Here is the abstract of my
paper:
"A novel memory with limited processing power and internal connectivity
at each element is proposed. This memory carries out parallel processing
within itself. Many common algorithms using this memory are discussed. For
an array of N items, it reduces the total instruction cycle count of
universal operations such as insertion and match finding to ~ 1, local
operations such as filtering and pattern recognition to ~ local operation
size, and global operations such as sum and sorting to ~ sqrt(N).
Particularly, it eliminates most streaming activities for data processing
purpose on the data bus. Yet it remains general purposed, easy to use, pin
compatible with conventional memory, and practical for implementation. In
addition, some new designs, such as all-line decoder, general decoder,
parallel shifter, parallel comparator, parallel adder and parallel divider,
are presented."
Please drop a line to my email at: Chengpu@gmail.com
Regards,
Chengpu Wang |
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Terje Mathisen
Guest
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| Posted:
Fri Feb 04, 2005 7:56 am Post subject:
Re: A new computer architecture |
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Yingxia Wang wrote:
| Quote: | Dear All:
Please visit my site at:
http://mysite.verizon.net/~vze26krk/CPM.html
There, I will discuss the end of Moore's law, and a new computer
architecture with I have proposed in 2003. Here is the abstract of my
paper:
"A novel memory with limited processing power and internal connectivity
at each element is proposed. This memory carries out parallel processing
|
Dear Chengpu, if you had taken the trouble to browse comp.arch archives
for a few years, you would have seen that PIM (Processors In Memory) is
one of the recurring themes. :-)
It is, as always, a very obvious and intuitive idea, whose time will
probably never come. :-(
Economy of scaling means that making just some quite small changes to
regular memory arrays can make them _much_ more expensive.
BTW, my first exposure to PIM was when a university lecturer I had in
'Algorithms and Data Structures 2' told about an IBM patent (this was
around 1980, so the patent must have lapsed 10+ years ago!) for a
sorting memory array:
Stream data into it at full IO bandwidth, then immediately start
streaming the sorted results back out. Limited only by the size of the
sorting memory array itself.
For even larger sorts you would of course split the input into chunks,
then combine this with a merge step at the end.
| Quote: | within itself. Many common algorithms using this memory are discussed. For
an array of N items, it reduces the total instruction cycle count of
universal operations such as insertion and match finding to ~ 1, local
operations such as filtering and pattern recognition to ~ local operation
size, and global operations such as sum and sorting to ~ sqrt(N).
Particularly, it eliminates most streaming activities for data processing
purpose on the data bus. Yet it remains general purposed, easy to use, pin
compatible with conventional memory, and practical for implementation. In
addition, some new designs, such as all-line decoder, general decoder,
parallel shifter, parallel comparator, parallel adder and parallel divider,
are presented."
Please drop a line to my email at: Chengpu@gmail.com
|
You don't post to usenet and ask people to reply by email, unless you
expect a lot of replies, and volunteer to digest all the replies you do
get, and post the results back here.
Terje
--
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching" |
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Arrvindh Shriraman
Guest
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| Posted:
Sun Feb 06, 2005 10:06 pm Post subject:
Re: A new computer architecture |
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Dear Chungpu,
I did take a look at the version of the paper on the site. Unfortunately
it doesnt seem to have any microarchitect pics and it becomes very
difficult to understand ur exact architecture. On the face of it though
it sounds very similar to some of the work done by Peter Kogge at IBM in
1994 when they developed a hypercube PIM chip with SIMD programming
model. Before coming to the UofR i worked at a research organization in
India. and i would urge you to take a look at some of the publications
we have in
http://portal.acm.org/citation.cfm?id=1024298&coll=GUIDE&dl=GUIDE&CFID=38103253&CFTOKEN=37979452
ACM SIGARCH News titled "Memory In Processor - Supercomputer On a Chip".
I would need to have a close look at your work before commenting on it.
On the face of it though it sounds similar to some of the older PIM
designs such as Terasys. Your idea is interesting though i think it
might have limited applicability. Also compared to some of the works by
the PIM group at Notre Dame ur work seems similar to what they did with
PIM in the period 1993-1996 when Peter Kogge was at IBM in 1994. Take a
look at their PIM page. Will give u a more clear idea on this topic.
I have been working on this topic for the last few years and can help
you to refine the paper further. I think there's something in it. But is
it completely novel is the ?. A refined thinking with clear
understanding of PIM history will help sift out whats not novel and
claim and propose what u have done. This is what peeved the reviewers i
think.
Bye
Yingxia Wang wrote:
| Quote: | Dear All:
Please visit my site at:
http://mysite.verizon.net/~vze26krk/CPM.html
There, I will discuss the end of Moore's law, and a new computer
architecture with I have proposed in 2003. Here is the abstract of my
paper:
"A novel memory with limited processing power and internal connectivity
at each element is proposed. This memory carries out parallel processing
within itself. Many common algorithms using this memory are discussed. For
an array of N items, it reduces the total instruction cycle count of
universal operations such as insertion and match finding to ~ 1, local
operations such as filtering and pattern recognition to ~ local operation
size, and global operations such as sum and sorting to ~ sqrt(N).
Particularly, it eliminates most streaming activities for data processing
purpose on the data bus. Yet it remains general purposed, easy to use, pin
compatible with conventional memory, and practical for implementation. In
addition, some new designs, such as all-line decoder, general decoder,
parallel shifter, parallel comparator, parallel adder and parallel divider,
are presented."
Please drop a line to my email at: Chengpu@gmail.com
Regards,
Chengpu Wang
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Tim Clacy
Guest
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| Posted:
Mon Feb 07, 2005 5:54 pm Post subject:
Re: A new computer architecture |
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Terje Mathisen wrote:
| Quote: | Yingxia Wang wrote:
Dear All:
Please visit my site at:
http://mysite.verizon.net/~vze26krk/CPM.html
There, I will discuss the end of Moore's law, and a new computer
architecture with I have proposed in 2003. Here is the abstract of
my paper:
"A novel memory with limited processing power and internal
connectivity at each element is proposed. This memory carries out
parallel processing
Dear Chengpu, if you had taken the trouble to browse comp.arch
archives
for a few years, you would have seen that PIM (Processors In Memory)
is
one of the recurring themes. :-)
It is, as always, a very obvious and intuitive idea, whose time will
probably never come. :-(
|
That's a matter of opinion; processors in memory are already common-place in
the form of time-multiplexed VMs (multi-tasking kernels). Mr. Wang's idea
improves on the current situation by (1) doing in hardware what is currently
done by layer upon layer of software (2)introducing real concurrency and (3)
eliminating memory latency issues of 'legacy' CPU-memory systems.
| Quote: | Economy of scaling means that making just some quite small changes to
regular memory arrays can make them _much_ more expensive.
|
I too thought that this was a proposal to modify DRAM structure; however,
after reading the papers, you will see that this is not the case. Mr. Wang
is proposing a linked list of data-processing domains (1D or 2D depending on
the problem domain). This simple, repeating structure would utilize all
available chip real-estate productively, compared with 10% area for the CPU
and 90% for the mess to make the CPU appear to perform less badly. The
physical model maps directly common software models (active objects,
containers and algorithms, celllular automata, ...). The physical model of
CPU+memory does not map nicely to any practically useful software model
execept, perhaps, the simple-minded traditional 'computer program' (which
is, of course, all it was designed to do).
| Quote: | BTW, my first exposure to PIM was when a university lecturer I had in
'Algorithms and Data Structures 2' told about an IBM patent (this was
around 1980, so the patent must have lapsed 10+ years ago!) for a
sorting memory array:
Stream data into it at full IO bandwidth, then immediately start
streaming the sorted results back out. Limited only by the size of the
sorting memory array itself.
For even larger sorts you would of course split the input into chunks,
then combine this with a merge step at the end.
within itself. Many common algorithms using this memory are
discussed. For an array of N items, it reduces the total
instruction cycle count of universal operations such as insertion
and match finding to ~ 1, local operations such as filtering and
pattern recognition to ~ local operation size, and global operations
such as sum and sorting to ~ sqrt(N). Particularly, it eliminates
most streaming activities for data processing purpose on the data
bus. Yet it remains general purposed, easy to use, pin compatible
with conventional memory, and practical for implementation. In
addition, some new designs, such as all-line decoder, general
decoder, parallel shifter, parallel comparator, parallel adder and
parallel divider, are presented."
Please drop a line to my email at: Chengpu@gmail.com
You don't post to usenet and ask people to reply by email, unless you
expect a lot of replies, and volunteer to digest all the replies you
do
get, and post the results back here.
Terje |
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Nick Maclaren
Guest
|
| Posted:
Mon Feb 07, 2005 7:22 pm Post subject:
Re: A new computer architecture |
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|
In article <4207651e$0$236$edfadb0f@dread12.news.tele.dk>,
"Tim Clacy" <nospamtcl@nospamphaseone.nospamdk> writes:
|> Terje Mathisen wrote:
|> >
|> > Dear Chengpu, if you had taken the trouble to browse comp.arch
|> > archives
|> > for a few years, you would have seen that PIM (Processors In Memory)
|> > is
|> > one of the recurring themes. :-)
|> >
|> > It is, as always, a very obvious and intuitive idea, whose time will
|> > probably never come. :-(
I agree, though I differ on the reasons for that :-)
|> That's a matter of opinion; processors in memory are already common-place in
|> the form of time-multiplexed VMs (multi-tasking kernels). Mr. Wang's idea
|> improves on the current situation by (1) doing in hardware what is currently
|> done by layer upon layer of software (2)introducing real concurrency and (3)
|> eliminating memory latency issues of 'legacy' CPU-memory systems.
That is stretching the term "processors in memory" to the point that
I am waiting for the "ping" as it snaps.
|> > Economy of scaling means that making just some quite small changes to
|> > regular memory arrays can make them _much_ more expensive.
|>
|> I too thought that this was a proposal to modify DRAM structure; however,
|> after reading the papers, you will see that this is not the case. Mr. Wang
|> is proposing a linked list of data-processing domains (1D or 2D depending on
|> the problem domain).
That's been a recurring theme, too.
|> This simple, repeating structure would utilize all
|> available chip real-estate productively, compared with 10% area for the CPU
|> and 90% for the mess to make the CPU appear to perform less badly. The
|> physical model maps directly common software models (active objects,
|> containers and algorithms, celllular automata, ...).
Oh, really? Look a little harder. To a great extent, it is a very
similar model to MPI, and the MPI community knows a great deal about
the (considerable) advantages of that model and its (considerable)
disadvantages.
I am not putting down this model, which I agree is an excellent one,
but I am pointing out that it is neither new nor as simple to introduce
as you imply. I think that Terje agrees with both points :-)
Regards,
Nick Maclaren. |
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Stefan Monnier
Guest
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| Posted:
Mon Feb 07, 2005 8:50 pm Post subject:
Re: A new computer architecture |
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|
| Quote: | Dear Chengpu, if you had taken the trouble to browse comp.arch archives for
a few years, you would have seen that PIM (Processors In Memory) is one of
the recurring themes. :-)
It is, as always, a very obvious and intuitive idea, whose time will
probably never come. :-(
|
I don't quite agree. The way I see it, we indeed will never "switch to
PIM", but we've been sliding slowly towards the PIM model and I don't see
this trend stopping any time soon.
I.e. instead of moving the CPU onto the memory chip, we just slowly move the
memory closer to the ever-smaller CPU. Things like:
- look at the proportion of chip real estate used for cache (aka memory).
- Opteron-style systems, where the memory is still off-chip, but is already
more closely attached to its CPU than the CPUs are attached together,
compared to typical SMP.
Maybe the deciding factor of whether something is PIM or not is whether each
memory chip has a CPU on-board, and I don't know if or when we'll get there,
but I see no reason why we wouldn't be able to get there in very small
evolutional steps such that by the time we get there nobody noticed that we
actually "switched to PIM". The important part being that people will have
had plenty of time to slowly adjust their C&Cobol&PL/1 programs.
Stefan |
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