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Elder Costa · Guest

Hello.

I am using Xilinx ISE Foundation 6.3i. I am trying to implement a sine
lookup table (targeted at either SpartanIII or VirtexII) but I am
getting a strange result when running functional simulation (testbench
bellow) with Modelsim: instead of showing the first element from the
array on the output after the first rising edge it shows the 12th.
Everithing happens as if I had initialized the address counter with 11
instead of 0. I know I am making a basic mistake but I cannot figure
out where or why.

--------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sintab20 is
Port (
i_Clk : in std_logic;
i_En : in std_logic;
i_Addr : in integer range 0 to 19;
o_DataOut : out std_logic_vector(17 downto 0)
);
end sintab20;

architecture Behavioral of sintab20 is
subtype t_ROM_DATA is std_logic_vector(17 downto 0);
type t_ROM_TYPE is array (natural range <>) of t_ROM_DATA;
constant k_SinTab20x1: t_ROM_TYPE(19 downto 0) :=
(
"000000000000000000",
"001001111000110111",
"010010110011110010",
"011001111000110111",
"011110011011110000",
"011111111111111111",
"011110011011110000",
"011001111000110111",
"010010110011110010",
"001001111000110111",
"000000000000000000",
"110110000111001001",
"101101001100001110",
"100110000111001001",
"100001100100010000",
"100000000000000001",
"100001100100010000",
"100110000111001001",
"101101001100001110",
"110110000111001001"
);

begin
process (i_Clk)
begin
if rising_edge(i_Clk) then
if (i_En = '1') then
o_DataOut <= k_SinTab20x1(i_Addr);
end if;
end if;
end process;
end Behavioral;

-------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY sintab20_tb IS
END sintab20_tb;

ARCHITECTURE behavior OF sintab20_tb IS

COMPONENT sintab20
PORT(
i_Clk : IN std_logic;
i_En : IN std_logic;
i_Addr : IN integer range 0 to 19;
o_DataOut : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;

SIGNAL i_Clk : std_logic;
SIGNAL i_En : std_logic;
SIGNAL i_Addr : integer range 0 to 19;
SIGNAL o_DataOut : std_logic_vector(17 downto 0);
constant k_PERIOD : time := 20 ns;

BEGIN

uut: sintab20 PORT MAP(
i_Clk => i_Clk,
i_En => i_En,
i_Addr => i_Addr,
o_DataOut => o_DataOut
);
-- *** Test Bench - User Defined Section ***
i_En <= '1';
-- clock
process
begin
for i in 0 to 40 loop
i_Clk <= '0';
wait for k_PERIOD/2;
i_Clk <= '1';
wait for k_PERIOD/2;
end loop;
wait;
end process;

-- address counter
process
begin
i_Addr <= 0;
wait for k_PERIOD*2;
for i in 0 to 40 loop
if i_Addr < 19 then
i_Addr <= i_Addr + 1;
else
i_Addr <= 0;
end if;
wait for k_PERIOD;
end loop;
wait;
end process;
-- *** End Test Bench - User Defined Section ***
END;

--------------

TIA for your comments.

Elder.

Mike Treseler · Guest

Your main test process executes in zero sim time.
Consider synchronizing the process as shown below.

-- Mike Treseler
--_______________________________________

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sintab20 is
port (
i_Clk : in std_logic;
i_En : in std_logic;
i_Addr : in integer range 0 to 19;
o_DataOut : out std_logic_vector(17 downto 0)
);
end sintab20;

architecture Behavioral of sintab20 is
subtype t_ROM_DATA is std_logic_vector(17 downto 0);

type t_ROM_TYPE is array (natural range <>) of t_ROM_DATA;

constant k_SinTab20x1 : t_ROM_TYPE(19 downto 0) :=
(
"000000000000000000",
"001001111000110111",
"010010110011110010",
"011001111000110111",
"011110011011110000",
"011111111111111111",
"011110011011110000",
"011001111000110111",
"010010110011110010",
"001001111000110111",
"000000000000000000",
"110110000111001001",
"101101001100001110",
"100110000111001001",
"100001100100010000",
"100000000000000001",
"100001100100010000",
"100110000111001001",
"101101001100001110",
"110110000111001001"
);

begin
process (i_Clk)
begin
if rising_edge(i_Clk) then
if (i_En = '1') then
o_DataOut <= k_SinTab20x1(i_Addr);
end if;
end if;
end process;
end Behavioral;

----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sintab20_tb is
end entity sintab20_tb;

architecture sim of sintab20_tb is
-- Fri Dec 10 10:34:08 2004 Mike
-- component ports
signal i_Clk_s : std_logic; -- [in]
signal i_En_s : std_logic; -- [in]
signal i_Addr_s : integer range 0 to 19; -- [in]
signal o_DataOut_s : std_logic_vector(17 downto 0); -- [out]

-- run with waves:
-- vsim sintab20_tb -do "add wave -r /*;run -all;"

signal done_s : boolean;
signal clk_s : std_ulogic;
signal rst_s : std_ulogic;
begin -- architecture sim

-- component instantiation
DUT : entity work.sintab20
port map (i_Clk => i_Clk_s, -- [in]
i_En => i_En_s, -- [in]
i_Addr => i_Addr_s, -- [in]
o_DataOut => o_DataOut_s); -- [out]
i_clk_s <= clk_s;

-- clock generation
tb_clk : process is
constant clk_cy : time := 20 ns;
begin
clk_s <= '0'; -- clk low during rst
if now < clk_cy then
rst_s <= '1'; -- rst high once
else
rst_s <= '0'; -- then low forever
wait for clk_cy/2; -- clk low phase
clk_s <= '1';
end if;
if done_s then wait;
end if;
wait for clk_cy/2; -- clk or rst high phase
end process tb_clk;

main : process (clk_s, rst_s) is
constant last_step_v : natural := 19;
variable step_v : natural;
begin
clked : if rst_s = '1' then
step_v := 1;
elsif rising_edge(clk_s) then
done_s <= step_v > last_step_v;
i_Addr_s <= 0;
enable : if not done_s then
i_En_s <= '1';
i_Addr_s <= step_v - 1;
step_v := step_v + 1; -- step counter
end if enable;
end if clked;
end process main;

end architecture sim;

glen herrmannsfeldt · Guest

Elder Costa wrote:

Elder Costa · Guest

glen herrmannsfeldt wrote:

Elder Costa · Guest

Mike Treseler wrote:

glen herrmannsfeldt · Guest

Elder Costa wrote:

(snip regarding sin lookup tables)

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