Clock Gating !!!

[Chandrasekhar]

Hi All,

I m facing some problems with clock gating in Virtex II FPGA
using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not
completely routable. I know that clock gating in an FPGA is not
advisable, but my requirement is like that. I have total 15 clocks of 5
diffterent frequencies. All these 15 clocks are gated with gate enable
before going to the individual modules. The gating must be done in my
clock tree module only.

Can anyone please give some inputs on this... Any help will
be greatly appreciated.

Thanks...
Chandrasekhar.

[Hendra]

I assume you have gated clock because you want to suspend the operation
of some sequential logics when you want it. If that's what you want,
instead of having gated clock, you can have "clock enable". The
following example explains what I mean by "clock enable"

Let's say you want to have a 4 bit counter, but you want to stop the
counter from counting when you want it. You can do it this way
always @(posedge clk)
begin
if (clock_enable)
counter <= counter + 1;
else
counter <= counter;
end

This way, your counter is completely synchronous and still having the
ability to make the counter to stop counting by driving clock_enable to
low.

The same technique can be used to slow down your sequential logics,
without having to have multiple clocks in your design.
For example:
Let's say you want to have 2 seperate DFFs, one runs at 50 MHz and the
other runs at 100 MHz. Instead of having two different clocks in your
system, you can just have one clock, runs at 100 MHz.

reg [1:0]clock_divide;

always @(posedge clk)
begin
clock_divide <= clock_divide + 1;
end

//DFF 1
always @(posedge clk)
begin
if (clock_enable[1])
q1 <= d1;
else
q1 <= q1;
end

//DFF 2
always @(posedge clk)
begin
q2 <= d2;
end

This way, your DFF2 runs at 100 MHz, while your DFF1 runs at 50 MHz.
Both DFFs run at different frequencies, without having to have 2
different clocks.


Hendra

[Hendra]

CORRECTION:

The second example should be:

reg [1:0]clock_enable;
always @(posedge clk)
begin
clock_enable <= clock_enable + 1;
end

[Symon]

"Chandrasekhar" <chandu_419@yahoo.com> wrote in message
news:1102489026.603341.150020@c13g2000cwb.googlegroups.com...

Hi All,

I m facing some problems with clock gating in Virtex II FPGA
using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not
completely routable. I know that clock gating in an FPGA is not
advisable, but my requirement is like that.

No it isn't. Use enables instead. The tool has saved you from months of pain
by refusing to connect up such an abomination!

I have total 15 clocks of 5
diffterent frequencies. All these 15 clocks are gated with gate enable
before going to the individual modules. The gating must be done in my
clock tree module only.

Can anyone please give some inputs on this... Any help will
be greatly appreciated.

Thanks...
Chandrasekhar.

Fix it so you have one clock. Make it faster than the others; why not use a
DCM to create it? Use enables for your original 15 clocks. If necessary,
retime the stuff from the various clock domains on the way in, and on the
way out, in your 'clock tree module'. A little thought up front will save
you so many problems. Here's a resynchronising circuit posted by Rick
Collins to get you going.
http://www.fpga-faq.com/archives/59400.html#59400

Good luck, Syms.

[Guest]

I m facing some problems with clock gating in Virtex II FPGA
using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not
completely routable. I know that clock gating in an FPGA is not
advisable, but my requirement is like that. I have total 15 clocks of
5
diffterent frequencies. All these 15 clocks are gated with gate
enable
before going to the individual modules. The gating must be done in my
clock tree module only.

Can anyone please give some inputs on this... Any help will
be greatly appreciated.

SynplifyPro has an option to automatically convert gated clocks into
clock enables. Very useful for ASIC prototyping.

Cheers,
Jon